Users Guide
TMS320DM644x DMSoC VLYNQ Port
SPRUE36A -September
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Contents
VLYNQ 2.0 Packet Format
Contents
Supported Ordered Sets
VLYNQ 2.X Packets
List of Figures
List of Tables
List of Tables
About This Document
Read This First
Preface
Notational Conventions
Trademarks
VLYNQ is a trademark of Texas Instruments
1.2 Features
VLYNQ Port
Users Guide
1 Introduction
1.4 Industry Standards Compliance Statement
1.3 Functional Block Diagram
Figure 1. VLYNQ Port Functional Block Diagram
2 Peripheral Architecture
Figure 2. External Clock Block Diagram
Figure 3. Internal Clock Block Diagram
2.1 Clock Control
2.3 Pin Multiplexing
2.2 Signal Descriptions
Table 1. VLYNQ Port Pins
2.4 Protocol Description
2.5 VLYNQ Functional Description
Figure 4. VLYNQ Module Structure
2.5.1 Write Operations
Figure 5. Write Operations
2.5.2 Read Operations
Figure 6. Read Operations
2.7 Auto-Negotiation
2.8 Serial Interface Width Configuration
2.6 Initialization
Table 2. Serial Interface Width
2.9 Address Translation
Figure 7. Example Address Memory Map
Table 3. Address Translation Example Single Mapped Region
Table 4. Address Translation Example Single Mapped Region
DM644x VLYNQ Module
Remote VLYNQ Module
Remote VLYNQ Module
See Appendix A
2.10 Flow Control
Example 1. Address Translation Example
2.11.2 Hardware Reset Considerations
2.11 Reset Considerations
2.11.1 Software Reset Considerations
2.12 Interrupt Support
Figure 8. Interrupt Generation Mechanism Block Diagram
2.12.2 Writes to Interrupt Pending/Set Register
2.12.3 Remote Interrupts
2.12.4 Serial Bus Error Interrupts
2.13 DMA Event Support
2.14 Power Management
2.15 Emulation Considerations
Table 6. VLYNQ Port Controller Registers
3 VLYNQ Port Registers
Table 5. VLYNQ Register Address Space
Table 7. Revision Register REVID Field Descriptions
3.1 Revision Register REVID
Figure 9. Revision Register REVID
VLYNQ Port Registers
Table 8. Control Register CTRL Field Descriptions
3.2 Control Register CTRL
Figure 10. Control Register CTRL
VLYNQ Port Registers
Field
Table 8. Control Register CTRL Field Descriptions continued
VLYNQ Port Registers
Description
Table 9. Status Register STAT Field Descriptions
3.3 Status Register STAT
Figure 11. Status Register STAT
VLYNQ Port Registers
Field
Table 9. Status Register STAT Field Descriptions continued
VLYNQ Port Registers
Description
Figure 12. Interrupt Priority Vector Status/Clear Register INTPRI
3.4 Interrupt Priority Vector Status/Clear Register INTPRI
3.5 Interrupt Status/Clear Register INTSTATCLR
Figure 13. Interrupt Status/Clear Register INTSTATCLR
Figure 14. Interrupt Pending/Set Register INTPENDSET
3.6 Interrupt Pending/Set Register INTPENDSET
3.7 Interrupt Pointer Register INTPTR
Figure 15. Interrupt Pointer Register INTPTR
Table 14. Address Map Register XAM Field Descriptions
3.8 Transmit Address Map Register XAM
Figure 16. Transmit Address Map Register XAM
VLYNQ Port Registers
Figure 17. Receive Address Map Size 1 Register RAMS1
3.9 Receive Address Map Size 1 Register RAMS1
3.10 Receive Address Map Offset 1 Register RAMO1
Figure 18. Receive Address Map Offset 1 Register RAMO1
Figure 19. Receive Address Map Size 2 Register RAMS2
3.11 Receive Address Map Size 2 Register RAMS2
3.12 Receive Address Map Offset 2 Register RAMO2
Figure 20. Receive Address Map Offset 2 Register RAMO2
Figure 21. Receive Address Map Size 3 Register RAMS3
3.13 Receive Address Map Size 3 Register RAMS3
3.14 Receive Address Map Offset 3 Register RAMO3
Figure 22. Receive Address Map Offset 3 Register RAMO3
Figure 23. Receive Address Map Size 4 Register RAMS4
3.15 Receive Address Map Size 4 Register RAMS4
3.16 Receive Address Map Offset 4 Register RAMO4
Figure 24. Receive Address Map Offset 4 Register RAMO4
Figure 25. Chip Version Register CHIPVER
3.17 Chip Version Register CHIPVER
3.18 Auto Negotiation Register AUTNGO
Table 23. Chip Version Register CHIPVER Field Descriptions
Remote Configuration Registers
4 Remote Configuration Registers
Table 25. VLYNQ Port Remote Controller Registers
A.2 Supported Ordered Sets
Appendix A VLYNQ Protocol Specifications
A.1 Special 8b/10b Code Groups
Table A-1. Special 8b/10b Code Groups
Figure A-1. Packet Format 10-bit Symbol Representation
A.3 VLYNQ 2.0 Packet Format
Table A-3. Packet Format 10-bit Symbol Representation Description
A.4 VLYNQ 2.X Packets
VLYNQ 2.X Packets
A command, length, address, and start receive data from the idle stream. A flow enable was received for the command channel, but there is data to return, so the flow is followed by a channel 1 descriptor the command for return data actually indicates a channel 1, and the channel 1 packet is now under way. A flow is now received for channel 1, but it is soon disabled so the channel 1 packet continues. The flow is enabled for channel one again, quickly after flow is released for channel 0, so the data continues for channel 0 when a flow is received again for channel 0. Channel 0 then receives a flow disable, completes its packet, followed by channel 1 flow disable, where the channel 1 packet is also completed
Appendix B Write/Read Performance
B.1 Write Performance
Burst Size in 32-bit words
Table B-1. Scaling Factors
Write Performance
Data Bytes
B.2 Read Performance
Table B-3. Relative Performance with Various Latencies
Appendix C
Appendix C Revision History
Table C-1. Document Revision History
Additions/Modifications/Deletions
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