Users Guide | Texas Instruments VLYNQ Port instruction

TMS320DM644x DMSoC

VLYNQ Port

User's Guide

Literature Number: SPRUE36A

September 2007

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Texas Instruments VLYNQ Port manual Users Guide

Contents

Users Guide Submit Documentation Feedback Contents Appendix C Appendix B List of Figures List of Tables Notational Conventions About This DocumentRelated Documentation From Texas Instruments Trademarks Introduction FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block Diagram Clock Control Peripheral Architecture Vlynq Port Pins Signal DescriptionsPin Multiplexing Protocol Description Vlynq Module Structure Vlynq Functional Description TxSM Write Operations Read Operations Initialization Serial Interface Width ConfigurationAuto-Negotiation Serial Interface Width Address Translation Register DM644x Vlynq Module Address Translation Example Single Mapped Region Remote Vlynq Module DM644x Vlynq Module Example 1. Address Translation Example Flow Control Software Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt Support Writes to Interrupt Pending/Set Register Interrupt Generation Mechanism Block Diagram DMA Event Support Serial Bus Error InterruptsRemote Interrupts Emulation Considerations Power Management Vlynq Register Address Space Vlynq Port RegistersVlynq Port Controller Registers Block Name Start Address End Address Size Revision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value Description Control Register Ctrl Field Descriptions Control Register Ctrl Bit Field Aoptdisable Status Register Stat Field Descriptions Status Register Stat Lerror No error Interrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend Instat Interrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions Intset Address Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1 Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2 Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3 Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4 Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field Descriptions Vlynq Port Remote Controller Registers Remote Configuration Registers Special 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSupported Ordered Sets Table A-1. Special 8b/10b Code Groups Vlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol Representation Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read Performance Burst Size in 32-bit words Data Bytes Table B-1. Scaling FactorsBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/sec Table B-3. Relative Performance with Various Latencies Read Performance Table C-1. Document Revision History Appendix C Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid