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Texas Instruments VLYNQ Port Functional Block Diagram, Industry Standards Compliance Statement

Models: VLYNQ Port

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1.3Functional Block Diagram

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Introduction

∙Symmetric Operations

–Transmit (TX) pins on the first device connect to the receive (RX) pins on the second device and vice-versa.

–Data pin widths are automatically detected after reset

–Re-request packets, response packets, and flow control information are all multiplexed and sent across the same physical pins.

–Supports both host/peripheral and peer-to-peer communication models

∙Simple block code packet formatting (8b/10b)

∙Supports in-band and flow control

–No extra pins are needed

–Allows the receiver to momentarily throttle the transmitter back when overflow is about to occur

–Uses the special built-in block code capability to interleave flow control information seamlessly with user data

∙Automatic packet formatting optimizations

∙Internal loopback modes are provided

∙Connects to legacy VLYNQ devices

1.3Functional Block Diagram

Figure 1 shows a functional block diagram of the VLYNQ port.

Figure 1. VLYNQ Port Functional Block Diagram

ARM/EDMA

System memory

VLYNQregister

access

CPU/EDMA initiated

transfersto

remotedevice

Offchip

(remote)

deviceaccess

VLYNQmodule

Slave config bus Interface

Master

config

bus

Interface

VLQINT

INT31

ARMinterrupt

controller

VLYNQ_SCRUN

VLYNQ_CLOCK

VLYNQ_TXD[3:0]

VLYNQ_RXD[3:0]

1.4Industry Standard(s) Compliance Statement

VLYNQ is an interface defined by Texas Instruments and does not conform to any other industry standard.

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VLYNQ Port

SPRUE36A –September 2007

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Texas Instruments VLYNQ Port manual Functional Block Diagram, Industry Standards Compliance Statement

Contents

Users Guide TMS320DM644x DMSoC VLYNQ PortSPRUE36A -September Submit Documentation FeedbackContents VLYNQ 2.0 Packet Format ContentsSupported Ordered Sets VLYNQ 2.X PacketsList of Figures List of Tables List of TablesAbout This Document Read This FirstPreface Notational ConventionsTrademarks VLYNQ is a trademark of Texas Instruments1.2 Features VLYNQ PortUsers Guide 1 IntroductionFigure 1. VLYNQ Port Functional Block Diagram 1.3 Functional Block Diagram1.4 Industry Standards Compliance Statement 2 Peripheral Architecture Figure 2. External Clock Block DiagramFigure 3. Internal Clock Block Diagram 2.1 Clock Control2.3 Pin Multiplexing 2.2 Signal DescriptionsTable 1. VLYNQ Port Pins 2.4 Protocol Description2.5 VLYNQ Functional Description Figure 4. VLYNQ Module Structure2.5.1 Write Operations Figure 5. Write Operations2.5.2 Read Operations Figure 6. Read Operations2.7 Auto-Negotiation 2.8 Serial Interface Width Configuration2.6 Initialization Table 2. Serial Interface Width2.9 Address Translation Figure 7. Example Address Memory Map Table 3. Address Translation Example Single Mapped RegionTable 4. Address Translation Example Single Mapped Region DM644x VLYNQ ModuleRemote VLYNQ Module Remote VLYNQ ModuleExample 1. Address Translation Example 2.10 Flow ControlSee Appendix A 2.11.2 Hardware Reset Considerations 2.11 Reset Considerations2.11.1 Software Reset Considerations 2.12 Interrupt SupportFigure 8. Interrupt Generation Mechanism Block Diagram 2.12.2 Writes to Interrupt Pending/Set Register2.13 DMA Event Support 2.12.4 Serial Bus Error Interrupts2.12.3 Remote Interrupts 2.14 Power Management 2.15 Emulation ConsiderationsTable 5. VLYNQ Register Address Space 3 VLYNQ Port RegistersTable 6. VLYNQ Port Controller Registers Table 7. Revision Register REVID Field Descriptions 3.1 Revision Register REVIDFigure 9. Revision Register REVID VLYNQ Port RegistersTable 8. Control Register CTRL Field Descriptions 3.2 Control Register CTRLFigure 10. Control Register CTRL VLYNQ Port RegistersField Table 8. Control Register CTRL Field Descriptions continuedVLYNQ Port Registers DescriptionTable 9. Status Register STAT Field Descriptions 3.3 Status Register STATFigure 11. Status Register STAT VLYNQ Port RegistersField Table 9. Status Register STAT Field Descriptions continuedVLYNQ Port Registers DescriptionFigure 12. Interrupt Priority Vector Status/Clear Register INTPRI 3.4 Interrupt Priority Vector Status/Clear Register INTPRI3.5 Interrupt Status/Clear Register INTSTATCLR Figure 13. Interrupt Status/Clear Register INTSTATCLRFigure 14. Interrupt Pending/Set Register INTPENDSET 3.6 Interrupt Pending/Set Register INTPENDSET3.7 Interrupt Pointer Register INTPTR Figure 15. Interrupt Pointer Register INTPTRTable 14. Address Map Register XAM Field Descriptions 3.8 Transmit Address Map Register XAMFigure 16. Transmit Address Map Register XAM VLYNQ Port RegistersFigure 17. Receive Address Map Size 1 Register RAMS1 3.9 Receive Address Map Size 1 Register RAMS13.10 Receive Address Map Offset 1 Register RAMO1 Figure 18. Receive Address Map Offset 1 Register RAMO1Figure 19. Receive Address Map Size 2 Register RAMS2 3.11 Receive Address Map Size 2 Register RAMS23.12 Receive Address Map Offset 2 Register RAMO2 Figure 20. Receive Address Map Offset 2 Register RAMO2Figure 21. Receive Address Map Size 3 Register RAMS3 3.13 Receive Address Map Size 3 Register RAMS33.14 Receive Address Map Offset 3 Register RAMO3 Figure 22. Receive Address Map Offset 3 Register RAMO3Figure 23. Receive Address Map Size 4 Register RAMS4 3.15 Receive Address Map Size 4 Register RAMS43.16 Receive Address Map Offset 4 Register RAMO4 Figure 24. Receive Address Map Offset 4 Register RAMO4Figure 25. Chip Version Register CHIPVER 3.17 Chip Version Register CHIPVER3.18 Auto Negotiation Register AUTNGO Table 23. Chip Version Register CHIPVER Field DescriptionsTable 25. VLYNQ Port Remote Controller Registers 4 Remote Configuration RegistersRemote Configuration Registers A.2 Supported Ordered Sets Appendix A VLYNQ Protocol SpecificationsA.1 Special 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation A.3 VLYNQ 2.0 Packet FormatTable A-3. Packet Format 10-bit Symbol Representation Description A.4 VLYNQ 2.X Packets VLYNQ 2.X PacketsA command, length, address, and start receive data from the idle stream. A flow enable was received for the command channel, but there is data to return, so the flow is followed by a channel 1 descriptor the command for return data actually indicates a channel 1, and the channel 1 packet is now under way. A flow is now received for channel 1, but it is soon disabled so the channel 1 packet continues. The flow is enabled for channel one again, quickly after flow is released for channel 0, so the data continues for channel 0 when a flow is received again for channel 0. Channel 0 then receives a flow disable, completes its packet, followed by channel 1 flow disable, where the channel 1 packet is also completed Appendix B Write/Read Performance B.1 Write PerformanceBurst Size in 32-bit words Table B-1. Scaling FactorsWrite Performance Data BytesB.2 Read Performance Table B-3. Relative Performance with Various LatenciesAppendix C Appendix C Revision HistoryTable C-1. Document Revision History Additions/Modifications/DeletionsProducts power.ti.comIMPORTANT NOTICE Applications