Texas Instruments VLYNQ Port manual List of Figures

	List of Figures
1	VLYNQ Port Functional Block Diagram	10
2	External Clock Block Diagram	11
3	Internal Clock Block Diagram	11
4	VLYNQ Module Structure	13
5	Write Operations	14
6	Read Operations	15
7	Example Address Memory Map	18
8	Interrupt Generation Mechanism Block Diagram	22
9	Revision Register (REVID)	26
10	Control Register (CTRL)	27
11	Status Register (STAT)	29
12	Interrupt Priority Vector Status/Clear Register (INTPRI)	31
13	Interrupt Status/Clear Register (INTSTATCLR)	31
14	Interrupt Pending/Set Register (INTPENDSET)	32
15	Interrupt Pointer Register (INTPTR)	32
16	Transmit Address Map Register (XAM)	33
17	Receive Address Map Size 1 Register (RAMS1)	34
18	Receive Address Map Offset 1 Register (RAMO1)	34
19	Receive Address Map Size 2 Register (RAMS2)	35
20	Receive Address Map Offset 2 Register (RAMO2)	35
21	Receive Address Map Size 3 Register (RAMS3)	36
22	Receive Address Map Offset 3 Register (RAMO3)	36
23	Receive Address Map Size 4 Register (RAMS4)	37
24	Receive Address Map Offset 4 Register (RAMO4)	37
25	Chip Version Register (CHIPVER)	38
26	Auto Negotiation Register (AUTNGO)	38
A-1	Packet Format (10-bit Symbol Representation)	41

SPRUE36A –September 2007 List of Figures 5

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