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Texas Instruments VLYNQ Port manual Receive Address Map Size 2 Register RAMS2

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3.11 Receive Address Map Size 2 Register (RAMS2)

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VLYNQ Port Registers

3.11 Receive Address Map Size 2 Register (RAMS2)

The receive address map size 2 register (RAMS2) is used to identify the intended destination of inbound serial packets. The RAMS2 is shown in Figure 19 and described in Table 17.

Figure 19. Receive Address Map Size 2 Register (RAMS2)

31	2	1	0
RXADRSIZE2		Reserved
R/W-0			R-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 17. Receive Address Map Size 2 Register (RAMS2) Field Descriptions

Bit	Field	Value	Description
31-2	RXADRSIZE2	0-3FFF FFFFh	The RXADRSIZE2 field is used to determine if receive packets are destined for the second
			of four mapped address regions. RXADRSIZE2 is compared with the address contained in
			the receive packet. If the received packet address is less than the value in RXADRSIZE2,
			the packet address is added to the receive address map offset 2 register (RAMO2) to obtain
			the translated address.
1-0	Reserved	0	Reserved. Always read as 0. Writes have no effect.

3.12 Receive Address Map Offset 2 Register (RAMO2)

The receive address map offset 2 register (RAMO2) is used with the receive address map size 2 register (RAMS2) to translate receive packet addresses to local device configuration bus addresses. The RAMO2 is shown in Figure 20 and described in Table 18.

Figure 20. Receive Address Map Offset 2 Register (RAMO2)

31	2	1	0
RXADROFFSET2		Reserved
R/W-0			R-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 18. Receive Address Map Offset 2 Register (RAMO2) Field Descriptions

Bit	Field	Value	Description
31-2	RXADROFFSET2	0-3FFF FFFFh	The RXADROFFSET2 field is used with the receive address map size 2 register (RAMS2)
			to determine the translated address for serial data. If the received packet address is less
			than the value in RAMS2, the packet address is added to the contents of this register to
			obtain the translated address.
1-0	Reserved	0	Reserved. Always read as 0. Writes have no affect.

SPRUE36A –September 2007	VLYNQ Port	35
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Texas Instruments VLYNQ Port manual Receive Address Map Size 2 Register RAMS2, Receive Address Map Offset 2 Register RAMO2

Contents

TMS320DM644x DMSoC VLYNQ Port Users GuideSubmit Documentation Feedback SPRUE36A -SeptemberContents VLYNQ 2.X Packets ContentsSupported Ordered Sets VLYNQ 2.0 Packet FormatList of Figures List of Tables List of TablesNotational Conventions Read This FirstPreface About This DocumentVLYNQ is a trademark of Texas Instruments Trademarks1 Introduction VLYNQ PortUsers Guide 1.2 Features1.4 Industry Standards Compliance Statement 1.3 Functional Block DiagramFigure 1. VLYNQ Port Functional Block Diagram 2.1 Clock Control Figure 2. External Clock Block DiagramFigure 3. Internal Clock Block Diagram 2 Peripheral Architecture2.4 Protocol Description 2.2 Signal DescriptionsTable 1. VLYNQ Port Pins 2.3 Pin MultiplexingFigure 4. VLYNQ Module Structure 2.5 VLYNQ Functional DescriptionFigure 5. Write Operations 2.5.1 Write OperationsFigure 6. Read Operations 2.5.2 Read OperationsTable 2. Serial Interface Width 2.8 Serial Interface Width Configuration2.6 Initialization 2.7 Auto-Negotiation2.9 Address Translation Table 3. Address Translation Example Single Mapped Region Figure 7. Example Address Memory MapRemote VLYNQ Module DM644x VLYNQ ModuleRemote VLYNQ Module Table 4. Address Translation Example Single Mapped RegionSee Appendix A 2.10 Flow ControlExample 1. Address Translation Example 2.12 Interrupt Support 2.11 Reset Considerations2.11.1 Software Reset Considerations 2.11.2 Hardware Reset Considerations2.12.2 Writes to Interrupt Pending/Set Register Figure 8. Interrupt Generation Mechanism Block Diagram2.12.3 Remote Interrupts 2.12.4 Serial Bus Error Interrupts2.13 DMA Event Support 2.15 Emulation Considerations 2.14 Power ManagementTable 6. VLYNQ Port Controller Registers 3 VLYNQ Port RegistersTable 5. VLYNQ Register Address Space VLYNQ Port Registers 3.1 Revision Register REVIDFigure 9. Revision Register REVID Table 7. Revision Register REVID Field DescriptionsVLYNQ Port Registers 3.2 Control Register CTRLFigure 10. Control Register CTRL Table 8. Control Register CTRL Field DescriptionsDescription Table 8. Control Register CTRL Field Descriptions continuedVLYNQ Port Registers FieldVLYNQ Port Registers 3.3 Status Register STATFigure 11. Status Register STAT Table 9. Status Register STAT Field DescriptionsDescription Table 9. Status Register STAT Field Descriptions continuedVLYNQ Port Registers FieldFigure 13. Interrupt Status/Clear Register INTSTATCLR 3.4 Interrupt Priority Vector Status/Clear Register INTPRI3.5 Interrupt Status/Clear Register INTSTATCLR Figure 12. Interrupt Priority Vector Status/Clear Register INTPRIFigure 15. Interrupt Pointer Register INTPTR 3.6 Interrupt Pending/Set Register INTPENDSET3.7 Interrupt Pointer Register INTPTR Figure 14. Interrupt Pending/Set Register INTPENDSETVLYNQ Port Registers 3.8 Transmit Address Map Register XAMFigure 16. Transmit Address Map Register XAM Table 14. Address Map Register XAM Field DescriptionsFigure 18. Receive Address Map Offset 1 Register RAMO1 3.9 Receive Address Map Size 1 Register RAMS13.10 Receive Address Map Offset 1 Register RAMO1 Figure 17. Receive Address Map Size 1 Register RAMS1Figure 20. Receive Address Map Offset 2 Register RAMO2 3.11 Receive Address Map Size 2 Register RAMS23.12 Receive Address Map Offset 2 Register RAMO2 Figure 19. Receive Address Map Size 2 Register RAMS2Figure 22. Receive Address Map Offset 3 Register RAMO3 3.13 Receive Address Map Size 3 Register RAMS33.14 Receive Address Map Offset 3 Register RAMO3 Figure 21. Receive Address Map Size 3 Register RAMS3Figure 24. Receive Address Map Offset 4 Register RAMO4 3.15 Receive Address Map Size 4 Register RAMS43.16 Receive Address Map Offset 4 Register RAMO4 Figure 23. Receive Address Map Size 4 Register RAMS4Table 23. Chip Version Register CHIPVER Field Descriptions 3.17 Chip Version Register CHIPVER3.18 Auto Negotiation Register AUTNGO Figure 25. Chip Version Register CHIPVERRemote Configuration Registers 4 Remote Configuration RegistersTable 25. VLYNQ Port Remote Controller Registers Table A-1. Special 8b/10b Code Groups Appendix A VLYNQ Protocol SpecificationsA.1 Special 8b/10b Code Groups A.2 Supported Ordered SetsA.3 VLYNQ 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationTable A-3. Packet Format 10-bit Symbol Representation Description VLYNQ 2.X Packets A.4 VLYNQ 2.X PacketsA command, length, address, and start receive data from the idle stream. A flow enable was received for the command channel, but there is data to return, so the flow is followed by a channel 1 descriptor the command for return data actually indicates a channel 1, and the channel 1 packet is now under way. A flow is now received for channel 1, but it is soon disabled so the channel 1 packet continues. The flow is enabled for channel one again, quickly after flow is released for channel 0, so the data continues for channel 0 when a flow is received again for channel 0. Channel 0 then receives a flow disable, completes its packet, followed by channel 1 flow disable, where the channel 1 packet is also completed B.1 Write Performance Appendix B Write/Read PerformanceData Bytes Table B-1. Scaling FactorsWrite Performance Burst Size in 32-bit wordsTable B-3. Relative Performance with Various Latencies B.2 Read PerformanceAdditions/Modifications/Deletions Appendix C Revision HistoryTable C-1. Document Revision History Appendix CApplications power.ti.comIMPORTANT NOTICE Products