Appendix C Revision History | Texas Instruments VLYNQ Port specs

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Appendix C

Appendix C Revision History

Table C-1lists the changes made since the previous version of this document.

	Table C-1. Document Revision History
Reference	Additions/Modifications/Deletions
Section 2.9	Changed fourth paragraph.
	Added NOTE.
Table 8	Changed Description of INTLOCAL.
Section 3.17	Changed paragraph.
Figure 25	Changed DEVID reset value.
Table 23	Changed DEVID Description.
Figure A-1	Changed figure.
Table A-3	Changed Description of PKTTYPE[3:0] = 0110.
Table B-2	Changed table.
	Deleted Table B-3. Subsequent tables renumbered.

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Revision History

SPRUE36A –September 2007

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Texas Instruments VLYNQ Port manual Appendix C Revision History, Table C-1. Document Revision History

Contents

Users Guide Submit Documentation Feedback Contents Appendix B Appendix C List of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance Statement Peripheral Architecture Clock Control Signal Descriptions Vlynq Port PinsPin Multiplexing Protocol Description Vlynq Functional Description Vlynq Module Structure Write Operations TxSM Read Operations Serial Interface Width Configuration InitializationAuto-Negotiation Serial Interface Width Address Translation Address Translation Example Single Mapped Region Register DM644x Vlynq Module DM644x Vlynq Module Remote Vlynq Module Flow Control Example 1. Address Translation Example Reset Considerations Software Reset ConsiderationsHardware Reset Considerations Interrupt Support Interrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set Register Serial Bus Error Interrupts DMA Event SupportRemote Interrupts Power Management Emulation Considerations Vlynq Port Registers Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address Size Revision Register Revid Revision Register Revid Field DescriptionsRevmaj Revmin Bit Field Value Description Control Register Ctrl Control Register Ctrl Field Descriptions Aoptdisable Bit Field Status Register Stat Status Register Stat Field Descriptions No error Lerror Interrupt Priority Vector Status/Clear Register Intpri Interrupt Status/Clear Register IntstatclrNointpend Instat Interrupt Pending/Set Register Intpendset Interrupt Pointer Register IntptrInterrupt Pointer Register Intptr Field Descriptions Intset Transmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap Receive Address Map Size 1 Register RAMS1 Receive Address Map Offset 1 Register RAMO1RXADRSIZE1 RXADROFFSET1 Receive Address Map Size 2 Register RAMS2 Receive Address Map Offset 2 Register RAMO2RXADRSIZE2 RXADROFFSET2 Receive Address Map Size 3 Register RAMS3 Receive Address Map Offset 3 Register RAMO3RXADRSIZE3 RXADROFFSET3 Receive Address Map Size 4 Register RAMS4 Receive Address Map Offset 4 Register RAMO4RXADRSIZE4 RXADROFFSET4 Chip Version Register Chipver Auto Negotiation Register AutngoChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field Descriptions Remote Configuration Registers Vlynq Port Remote Controller Registers Appendix a Vlynq Protocol Specifications Special 8b/10b Code GroupsSupported Ordered Sets Table A-1. Special 8b/10b Code Groups Figure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet Format Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write Performance Table B-1. Scaling Factors Burst Size in 32-bit words Data BytesBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/sec Read Performance Table B-3. Relative Performance with Various Latencies Appendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid