Texas Instruments VLYNQ Port specification

www.ti.com

Peripheral Architecture

Figure 8. Interrupt Generation Mechanism Block Diagram

	Serialinterrupt
CPUwrites	packetfrom
	remotedevice
Serialbuserror
(LERROR/RERROR)	VLYNQcontrolregister(CTRL)
	VLYNQcontrolregister(CTRL)
VLYNQinterrupt	14	0
pending/setregister
(INTPENDSET)		INTLOCAL
INTLOCAL=1
	INTLOCAL=0

VLYNQ

Status/clear

register

(INTSTATCLR)

OR

VLQINT (ARMINT31)

Transmitserial

interruptpacket

For additional flexibility of interrupt handling, there is an interrupt priority vector status/clear register (INTPRI) that reports the highest priority interrupt asserted in the VLYNQ interrupt pending/set register (INTPENDSET) when INTLOCAL = 1. VLYNQ interprets bit 0 as the highest priority and it interprets bit 31 as the lowest priority. The value that is returned when read is the vector of the highest priority interrupt. Software can clear that interrupt by writing back the vector value. Additionally, INTRPRI provides a read-only status bit (NOINTPEND) to indicate whether or not there are any pending interrupts in the interrupt status/clear register (INTSTATCLR).

2.12.2Writes to Interrupt Pending/Set Register

As previously discussed, if the ARM CPU writes to the VLYNQ interrupt pending/set register (INTPENDSET), then depending on the value of the INTLOCAL bit in the VLYNQ control (CTRL) register, this will result in a local interrupt (to the device interrupt controller) or an interrupt packet transmitted over the serial interface to the remote device.

22

VLYNQ Port

SPRUE36A –September 2007

Submit Documentation Feedback

Image 22

Texas Instruments VLYNQ Port manual Interrupt Generation Mechanism Block Diagram, Writes to Interrupt Pending/Set Register

Contents

Users Guide Submit Documentation Feedback Contents Appendix B Appendix C List of Figures List of Tables Notational Conventions About This DocumentRelated Documentation From Texas Instruments Trademarks Introduction FeaturesPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance Statement Peripheral Architecture Clock Control Pin Multiplexing Signal DescriptionsVlynq Port Pins Protocol Description Vlynq Functional Description Vlynq Module Structure Write Operations TxSM Read Operations Auto-Negotiation Serial Interface Width ConfigurationInitialization Serial Interface Width Address Translation Address Translation Example Single Mapped Region Register DM644x Vlynq Module DM644x Vlynq Module Remote Vlynq Module Flow Control Example 1. Address Translation Example Hardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt Support Interrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set Register DMA Event Support Serial Bus Error InterruptsRemote Interrupts Power Management Emulation Considerations Vlynq Port Controller Registers Vlynq Port RegistersVlynq Register Address Space Block Name Start Address End Address Size Revmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value Description Control Register Ctrl Control Register Ctrl Field Descriptions Aoptdisable Bit Field Status Register Stat Status Register Stat Field Descriptions No error Lerror Nointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr Instat Interrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Intset Address Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1 RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2 RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3 RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4 Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field Descriptions Remote Configuration Registers Vlynq Port Remote Controller Registers Supported Ordered Sets Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code Groups Figure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet Format Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write Performance Burst Size Interface Running at 76.5 MHZ Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Bit Words Mbits/sec Mbytes/sec Read Performance Table B-3. Relative Performance with Various Latencies Table C-1. Document Revision History Appendix C Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid