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Texas Instruments VLYNQ Port manual Receive Address Map Size 4 Register RAMS4

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3.15 Receive Address Map Size 4 Register (RAMS4)

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VLYNQ Port Registers

3.15 Receive Address Map Size 4 Register (RAMS4)

The receive address map size 4 register (RAMS4) is used to identify the intended destination of inbound serial packets. The RAMS4 is shown in Figure 23 and described in Table 21.

Figure 23. Receive Address Map Size 4 Register (RAMS4)

31	2	1	0
RXADRSIZE4		Reserved
R/W-0			R-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 21. Receive Address Map Size 4 Register (RAMS4) Field Descriptions

Bit	Field	Value	Description
31-2	RXADRSIZE4	0-3FFF FFFFh	The RXADRSIZE4 field is used to determine if receive packets are destined for the fourth of
			four mapped address regions. RXADRSIZE4 is compared with the address contained in the
			receive packet. If the receive packet address is less than the value in RXADRSIZE4, the
			packet address is added to the receive address map offset 4 register (RAMO4) to obtain the
			translated address.
1-0	Reserved	0	Reserved. Always read as 0. Writes have no effect.

3.16 Receive Address Map Offset 4 Register (RAMO4)

The receive address map offset 4 register (RAMO4) is used with the receive address map size 4 register (RAMS4) to translate receive packet addresses to local device configuration bus addresses. The RAMS4 is shown in Figure 24 and described in Table 22.

Figure 24. Receive Address Map Offset 4 Register (RAMO4)

31	2	1	0
RXADROFFSET4		Reserved
R/W-0			R-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 22. Receive Address Map Offset 4 Register (RAMO4) Field Descriptions

Bit	Field	Value	Description
31-2	RXADROFFSET4	0-3FFF FFFFh	The RXADROFFSET4 field is used with the receive address map size 4 register (RAMS4)
			to determine the translated address for serial data. If the receive packet address is less
			than the value in RAMS4, the packet address is added to the contents of this register to
			obtain the translated address.
1-0	Reserved	0	Reserved. Always read as 0. Writes have no effect.

SPRUE36A –September 2007	VLYNQ Port	37
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Texas Instruments VLYNQ Port manual Receive Address Map Size 4 Register RAMS4, Receive Address Map Offset 4 Register RAMO4

Contents

TMS320DM644x DMSoC VLYNQ Port Users GuideSubmit Documentation Feedback SPRUE36A -SeptemberContents Supported Ordered Sets ContentsVLYNQ 2.0 Packet Format VLYNQ 2.X PacketsList of Figures List of Tables List of TablesPreface Read This FirstAbout This Document Notational ConventionsVLYNQ is a trademark of Texas Instruments TrademarksUsers Guide VLYNQ Port1.2 Features 1 IntroductionFigure 1. VLYNQ Port Functional Block Diagram 1.3 Functional Block Diagram1.4 Industry Standards Compliance Statement Figure 3. Internal Clock Block Diagram Figure 2. External Clock Block Diagram2 Peripheral Architecture 2.1 Clock ControlTable 1. VLYNQ Port Pins 2.2 Signal Descriptions2.3 Pin Multiplexing 2.4 Protocol DescriptionFigure 4. VLYNQ Module Structure 2.5 VLYNQ Functional DescriptionFigure 5. Write Operations 2.5.1 Write OperationsFigure 6. Read Operations 2.5.2 Read Operations2.6 Initialization 2.8 Serial Interface Width Configuration2.7 Auto-Negotiation Table 2. Serial Interface Width2.9 Address Translation Table 3. Address Translation Example Single Mapped Region Figure 7. Example Address Memory MapRemote VLYNQ Module DM644x VLYNQ ModuleTable 4. Address Translation Example Single Mapped Region Remote VLYNQ ModuleExample 1. Address Translation Example 2.10 Flow ControlSee Appendix A 2.11.1 Software Reset Considerations 2.11 Reset Considerations2.11.2 Hardware Reset Considerations 2.12 Interrupt Support2.12.2 Writes to Interrupt Pending/Set Register Figure 8. Interrupt Generation Mechanism Block Diagram2.13 DMA Event Support 2.12.4 Serial Bus Error Interrupts2.12.3 Remote Interrupts 2.15 Emulation Considerations 2.14 Power ManagementTable 5. VLYNQ Register Address Space 3 VLYNQ Port RegistersTable 6. VLYNQ Port Controller Registers Figure 9. Revision Register REVID 3.1 Revision Register REVIDTable 7. Revision Register REVID Field Descriptions VLYNQ Port RegistersFigure 10. Control Register CTRL 3.2 Control Register CTRLTable 8. Control Register CTRL Field Descriptions VLYNQ Port RegistersVLYNQ Port Registers Table 8. Control Register CTRL Field Descriptions continuedField DescriptionFigure 11. Status Register STAT 3.3 Status Register STATTable 9. Status Register STAT Field Descriptions VLYNQ Port RegistersVLYNQ Port Registers Table 9. Status Register STAT Field Descriptions continuedField Description3.5 Interrupt Status/Clear Register INTSTATCLR 3.4 Interrupt Priority Vector Status/Clear Register INTPRIFigure 12. Interrupt Priority Vector Status/Clear Register INTPRI Figure 13. Interrupt Status/Clear Register INTSTATCLR3.7 Interrupt Pointer Register INTPTR 3.6 Interrupt Pending/Set Register INTPENDSETFigure 14. Interrupt Pending/Set Register INTPENDSET Figure 15. Interrupt Pointer Register INTPTRFigure 16. Transmit Address Map Register XAM 3.8 Transmit Address Map Register XAMTable 14. Address Map Register XAM Field Descriptions VLYNQ Port Registers3.10 Receive Address Map Offset 1 Register RAMO1 3.9 Receive Address Map Size 1 Register RAMS1Figure 17. Receive Address Map Size 1 Register RAMS1 Figure 18. Receive Address Map Offset 1 Register RAMO13.12 Receive Address Map Offset 2 Register RAMO2 3.11 Receive Address Map Size 2 Register RAMS2Figure 19. Receive Address Map Size 2 Register RAMS2 Figure 20. Receive Address Map Offset 2 Register RAMO23.14 Receive Address Map Offset 3 Register RAMO3 3.13 Receive Address Map Size 3 Register RAMS3Figure 21. Receive Address Map Size 3 Register RAMS3 Figure 22. Receive Address Map Offset 3 Register RAMO33.16 Receive Address Map Offset 4 Register RAMO4 3.15 Receive Address Map Size 4 Register RAMS4Figure 23. Receive Address Map Size 4 Register RAMS4 Figure 24. Receive Address Map Offset 4 Register RAMO43.18 Auto Negotiation Register AUTNGO 3.17 Chip Version Register CHIPVERFigure 25. Chip Version Register CHIPVER Table 23. Chip Version Register CHIPVER Field DescriptionsTable 25. VLYNQ Port Remote Controller Registers 4 Remote Configuration RegistersRemote Configuration Registers A.1 Special 8b/10b Code Groups Appendix A VLYNQ Protocol SpecificationsA.2 Supported Ordered Sets Table A-1. Special 8b/10b Code GroupsA.3 VLYNQ 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationTable A-3. Packet Format 10-bit Symbol Representation Description VLYNQ 2.X Packets A.4 VLYNQ 2.X PacketsA command, length, address, and start receive data from the idle stream. A flow enable was received for the command channel, but there is data to return, so the flow is followed by a channel 1 descriptor the command for return data actually indicates a channel 1, and the channel 1 packet is now under way. A flow is now received for channel 1, but it is soon disabled so the channel 1 packet continues. The flow is enabled for channel one again, quickly after flow is released for channel 0, so the data continues for channel 0 when a flow is received again for channel 0. Channel 0 then receives a flow disable, completes its packet, followed by channel 1 flow disable, where the channel 1 packet is also completed B.1 Write Performance Appendix B Write/Read PerformanceWrite Performance Table B-1. Scaling FactorsBurst Size in 32-bit words Data BytesTable B-3. Relative Performance with Various Latencies B.2 Read PerformanceTable C-1. Document Revision History Appendix C Revision HistoryAppendix C Additions/Modifications/DeletionsIMPORTANT NOTICE power.ti.comProducts Applications