Texas Instruments VLYNQ Port Peripheral Architecture, Clock Control, External Clock Block Diagram

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Peripheral Architecture

2Peripheral Architecture

This section discusses the architecture and basic functions of the VLYNQ peripheral.

2.1Clock Control

The module'sserial clock direction and frequency are software configurable through the CLKDIR and CLKDIV bits in the VLYNQ control register (CTRL). The VLYNQ serial clock can be sourced from the internal system clock (CLKDIR = 1) or by an external clock source (CLKDIR = 0) for its serial operations.

The CLKDIV bit can divide the serial clock (1/1 - 1/8) down when the internal clock is selected as the source. The serial clock is not affected by the CLKDIV bit values, if the serial clock is externally sourced.

The reset value of the CLKDIR bit is 0 (external clock source).

The external clock source is shown in Figure 2. The internal clock source is shown in Figure 3.

Figure 2. External Clock Block Diagram

DMxxx￿device	VLYNQ￿device
	CLKDIR=0
VLYNQ	VLYNQ
	VLYNQ.CLK
	CLKDIR=0

Figure 3. Internal Clock Block Diagram

DMxxx￿device		VLYNQ￿device
	CLKDIR=1
VLYNQ		VLYNQ
VLYNQ
internal
sys￿clk	VLYNQ.CLK	Don't
		care
		CLKDIR=0

SPRUE36A –September 2007 VLYNQ Port 11

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