Register DM644x Vlynq Module | Texas Instruments VLYNQ Port specs

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Peripheral Architecture

Figure 7. Example Address Memory Map

		Remote
	DMxxxdevice(local)	VLYNQdevice
		0000:0000
		Mapregion1
	0400:0000
	(0C00:0000onCONFIGbus)
	Mapregion1	03FF:FFFF
	Mapregion1	0400:0000
		0400:0000
		Mapregion2
	07FF:FFFF	0400:00FF
	0800:0000
	Mapregion2
	0800:00FF	0500:0000
	0800:0100
	Mapregion3	Mapregion3
	0801:00FF	0500:FFFF
	0801:0100
	Mapregion4
		0B00:0000
	0841:00FF	Mapregion4
	0841:00FF
		0B3F:FFFF

The following shows an example illustrating the address translation used in each VLYNQ module. Address bits [31:26] are not used for address translation to remote devices on the DM644x device.

Table 3 illustrates address map register configuration when the DM644x device is transmitting data to the remote device.

Table 3. Address Translation Example (Single Mapped Region)

Register	DM644x VLYNQ Module	Remote VLYNQ Module
TX Address Map	0000 : 0000h	Do not care
RX Address Map Size 1	Do not care	0000 : 0100h
RX Address Map Offset 1	Do not care	0800 : 0000h

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VLYNQ Port

SPRUE36A –September 2007

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Texas Instruments VLYNQ Port manual Address Translation Example Single Mapped Region, Register DM644x Vlynq Module

Contents

Users Guide Submit Documentation Feedback Contents Appendix B Appendix C List of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance Statement Peripheral Architecture Clock Control Pin Multiplexing Signal DescriptionsVlynq Port Pins Protocol Description Vlynq Functional Description Vlynq Module Structure Write Operations TxSM Read Operations Auto-Negotiation Serial Interface Width ConfigurationInitialization Serial Interface Width Address Translation Address Translation Example Single Mapped Region Register DM644x Vlynq Module DM644x Vlynq Module Remote Vlynq Module Flow Control Example 1. Address Translation Example Hardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt Support Interrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set Register Serial Bus Error Interrupts DMA Event SupportRemote Interrupts Power Management Emulation Considerations Vlynq Port Controller Registers Vlynq Port RegistersVlynq Register Address Space Block Name Start Address End Address Size Revmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value Description Control Register Ctrl Control Register Ctrl Field Descriptions Aoptdisable Bit Field Status Register Stat Status Register Stat Field Descriptions No error Lerror Nointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr Instat Interrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Intset Transmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1 RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2 RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3 RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4 Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field Descriptions Remote Configuration Registers Vlynq Port Remote Controller Registers Supported Ordered Sets Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code Groups Figure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet Format Field Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write Performance Burst Size Interface Running at 76.5 MHZ Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Bit Words Mbits/sec Mbytes/sec Read Performance Table B-3. Relative Performance with Various Latencies Appendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid