Post Codes
The following are the InsydeH2O™ Functionality POST code tables. The components of the POST code table includes: SEC phase, PEI phase, DXE phase, BDS phase, CSM functions, S3 functions and ACPI functions.
Table 4-2. POST Code Range
Phase |
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| POST Code Range |
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SEC |
| 0x01 - 0x0F |
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PEI |
| 0x70 - 0x9F |
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DXE |
| 0x40 - 0x6F |
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BDS |
| 0x10 - 0x3F |
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SMM |
| 0xA0 - 0xBF |
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S3 |
| 0xC0 - 0xCF |
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ASL |
| 0x51 – 0x55 |
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| 0xE1 – 0xE4 |
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PostBDS |
| 0xF9 – 0xFE |
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InsydeH2ODDT™ Reserve |
| 0xD0 – 0xD7 |
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OEM Reserve |
| 0xE8 – 0xEB |
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Reserved |
| 0xD8 – 0xE0 |
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| 0xE5 – 0xE7 |
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| 0xEC – 0xF8 |
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Table |
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Functionality Name (Include\ | Phase | PostCod |
| Description | ||
PostCode.h) |
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SEC_SYSTEM_POWER_ON |
| SEC | 01 | CPU power on and switch to | ||
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| Protected mode | |
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SEC_BEFORE_MICROCODE_PATCH |
| SEC | 02 | Patching CPU microcode | ||
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SEC_AFTER_MICROCODE_PATCH |
| SEC | 03 | Setup Cache as RAM | ||
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SEC_ACCESS_CSR* |
| SEC | 04 | PCIE MMIO Base Address initial | ||
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SEC_GENERIC_MSRINIT* |
| SEC | 05 | CPU Generic MSR initialization | ||
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SEC_CPU_SPEEDCFG* |
| SEC | 06 | Setup CPU speed | ||
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SEC_SETUP_CAR_OK |
| SEC | 07 | Cache as RAM test | ||
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SEC_FORCE_MAX_RATIO* |
| SEC | 08 | Tune CPU frequency ratio to | ||
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| maximum level | |
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Troubleshooting |
