Operation Status Group

Bit

Programming the DC Source - 3

Table 3-1. Bit Configurations of Status Registers

Signal	Meaning
CAL	Operation Status Group
CAL	The dc source is computing new calibration constants
WTG	The dc source is waiting for a trigger
CV	The dc source is in constant voltage mode
CC+	The dc source is in constant current mode
CC-	The dc source is in negative constant current mode
OV	Questionable Status Group
OV	The overvoltage protection has tripped
OCP	The overcurrent protection has tripped
FS	The fuse is blown
OT	The overtemperature protection has tripped
RI	The remote inhibit state is active
Unreg	The output is unregulated
MeasOvld	Current measurement exceeded capability of low range
OPC	Standard Event Status Group
OPC	Operation complete
QYE	Query error
DDE	Device-dependent error
EXE	Execution error
CME	Command error
PON	Power-on
QUES	Status Byte and Service Request Enable Registers
QUES	Questionable status summary bit
MAV	Message Available summary bit
ESB	Event Status Summary bit
MSS	Master Status Summary bit
RQS	Request Service bit
OPER	Operation status summary bit

The Operation Status registers record signals that occur during normal operation. As shown below, the group consists of a Condition, PTR/NTR, Event, and Enable register. The outputs of the Operation Status register group are logically-ORed into the OPER(ation) summary bit (7) of the Status Byte register.

Condition

PTR Filter

NTR Filter

Event

Enable

Command

STAT:OPER:COND?

STAT:OPER:PTR <n>

STAT:OPER:NTR <n>

STAT:OPER:EVEN?

STAT:OPER:ENAB <n>

Description

A register that holds real-time status of the circuits being monitored. It is a read-only register.

A positive transistion filter that functions as described under STAT:OPER:NTRPTR commands in chapter 4. It is a read/write register.

A negative transition filter that functions as described under STAT:OPER:NTRPTR commands in chapter 4. It is a read/write register.

A register that latches any condition that is passed through the PTR or NTR filters. It is a read-only register that is cleared when read.

A register that functions as a mask for enabling specific bits from the Event register. It is a read/write register.

6613C, 66312A, 6631B, 6611C, 6614C specifications

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Agilent Technologies 6632B, 6634B, 66332A, 6633B, 6614C, 6613C, 6631B, 66312A Operation Status Group

Models: 6613C 66312A 6631B 6611C 6614C 6612C 6632B 6633B 66332A 6634B

Table 3-1. Bit Configurations of Status Registers

Signal

Meaning

CC+

OCP