Bit
0
5
8
10
11
0
1
2
4
9
10
14
0
2
3
4
5
7
3
4
5
6
7
Programming the DC Source - 3
Table 3-1. Bit Configurations of Status Registers
Signal | Meaning |
CAL | Operation Status Group |
The dc source is computing new calibration constants | |
WTG | The dc source is waiting for a trigger |
CV | The dc source is in constant voltage mode |
CC+ | The dc source is in constant current mode |
CC- | The dc source is in negative constant current mode |
OV | Questionable Status Group |
The overvoltage protection has tripped | |
OCP | The overcurrent protection has tripped |
FS | The fuse is blown |
OT | The overtemperature protection has tripped |
RI | The remote inhibit state is active |
Unreg | The output is unregulated |
MeasOvld | Current measurement exceeded capability of low range |
OPC | Standard Event Status Group |
Operation complete | |
QYE | Query error |
DDE | |
EXE | Execution error |
CME | Command error |
PON | |
QUES | Status Byte and Service Request Enable Registers |
Questionable status summary bit | |
MAV | Message Available summary bit |
ESB | Event Status Summary bit |
MSS | Master Status Summary bit |
RQS | Request Service bit |
OPER | Operation status summary bit |
Operation Status Group
The Operation Status registers record signals that occur during normal operation. As shown below, the group consists of a Condition, PTR/NTR, Event, and Enable register. The outputs of the Operation Status register group are
Register
Condition
PTR Filter
NTR Filter
Event
Enable
Command
STAT:OPER:COND?
STAT:OPER:PTR <n>
STAT:OPER:NTR <n>
STAT:OPER:EVEN?
STAT:OPER:ENAB <n>
Description
A register that holds
A positive transistion filter that functions as described under STAT:OPER:NTRPTR commands in chapter 4. It is a read/write register.
A negative transition filter that functions as described under STAT:OPER:NTRPTR commands in chapter 4. It is a read/write register.
A register that latches any condition that is passed through the PTR or NTR filters. It is a
A register that functions as a mask for enabling specific bits from the Event register. It is a read/write register.
33