CY7C68033/CY7C68034
Document #: 001-04247 Rev. *D Page 12 of 33
Pin Assignments
Figure9 and Figure10 identify all signals for the 56-pin
NX2LP-Flex package.
Three modes of operation are available for the NX2LP-Flex:
Port mode, GPIF Master mode, and Slave FIFO mode. These
modes define the signals on the right edge of each column in
Figure9. T he right-most column details the signal functionality
from the default NAND firmware image, which actually utilizes
GPIF Master mode. The signals on the left edge of the ‘Port’
column are common to all modes of the NX2LP-Flex. The
8051 selects the interface mode using the IFCONFIG[1:0]
register bits. Port mode is the power-on default configuration.
Figure10 details the pinout of the 56-pin package and lists pin
names for all modes of operation. Pin names with an asterisk
(*) feature programmable polarity.
Figure 9. Port and Signal Mapping
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDATA
DPLUS
DMINUS
→ RDY0
→ RDY1
← CTL0
← CTL1
←CTL2
↔ PA7
↔ PA6
↔ PA5
↔ PA4
↔ PA3/WU2
↔ PA2
↔ PA1/INT1#
↔ PA0/INT0#
↔ GPIO8
← GPIO9
↔ FD[15]
↔ FD[14]
↔ FD[13]
↔ FD[12]
↔ FD[11]
↔ FD[10]
↔ FD[9]
↔ FD[8]
↔ FD[7]
↔ FD[6]
↔ FD[5]
↔ FD[4]
↔ FD[3]
↔ FD[2]
↔ FD[1]
↔ FD[0]
→ SLRD
→ SLWR
← FLAGA
← FLAGB
← FLAGC
↔ FLAGD/SLCS#/PA7
↔ PKTEND
← FIFOADR1
↔ FIFOADR0
← PA3/WU2
← SLOE
← PA1/INT1#
↔ PA0/INT0#
↔ GPIO8
← GPIO9
↔ FD[15]
↔ FD[14]
↔ FD[13]
↔ FD[12]
↔ FD[11]
↔ FD[10]
↔ FD[9]
↔ FD[8]
↔ FD[7]
↔ FD[6]
↔ FD[5]
↔ FD[4]
↔ FD[3]
↔ FD[2]
↔ FD[1]
↔ FD[0]
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA7
PA6
PA5
PA4
WU2/PA3
PA2
INT1#/PA1
INTO#/PA0
GPIO8
GPIO9
Port GPIF Master Slave FIFO Default NAND
↔ CE7#/GPIO7
↔ CE6#/GPIO6
↔ CE5#/GPIO5
↔ CE4#/GPIO4
↔ CE3#/GPIO3
↔ CE2#/GPIO2
↔ CE1#
↔ CE0#
↔ DD7
↔ DD6
↔ DD5
↔ DD4
↔ DD3
↔ DD2
↔ DD1
↔ DD0
→ R_B1#
→ R_B2#
← WE#
← RE0#
← RE1#
← GPIO1
← GPIO0
← WP_SW#
← WP_NF#
← LED2#
→ LED1#
↔ ALE
↔ CLE
↔ GPIO8
← GPIO9
Firmware Use
[+] Feedback