CY7C68033/CY7C68034
Figure 10. CY7C68033/CY7C68034 56-pin QFN Pin Assignment
VCC *WAKEUP PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 GND GPIO9 VCC GND
RDY0/*SLRD
RDY1/*SLWR
AVCC XTALOUT XTALIN AGND AVCC
1
2
3
4
5
6
7
56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 |
CY7C68033/CY7C68034
45
44
43
42
41
40
39
38
37
36
RESET# GND PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/*WU2
DPLUS
DMINUS
AGND
VCC
GND
GPIO8
RESERVED#
8
9
10
11
12
13
14
15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 |
25
26
27
35
34
33
32
31
30
29
28
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC CTL2/*FLAGC CTL1/*FLAGB CTL0/*FLAGA
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
SDATA
SCL
Document #: | Page 13 of 33 |
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