Cypress CY7C68033, CY7C68034 Slave FIFO Asynchronous Address Figure 16. Slave FIFO Asynchronous Address Timing Diagram, Figure 18. Slave FIFO Asynchronous Read Sequence of Events Diagram

CY7C68033/CY7C68034
Document #: 001-04247 Rev. *D Page 28 of 33
Slave FIFO Asynchronous Address
Figure 16. Slave FIFO Asynchronous Address Timing Diagram[13]
Sequence Diagram
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 17. Slave FIFO Asynchronous Read Sequence and Timing Diagram[13]
Figure 18. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLRD/SLWR/PKTEND
SLCS/FIFOADR [1:0]
tSFA tFAH
Table 16.Slave FIFO Asynchronous Address Parameters[15]
Parameter Description Min. Max. Unit
tSFA FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time 10 ns
tFAH RD/WR/PKTEND to FIFOADR[1:0] Hold Time 10 ns
SLRD
FLAGS
SLOE
DATA
tRDpwh
tRDpwl
tOEon
tXFD
tXFLG
N
Data (X)
tXFD
N+1
tXFD
tOEoff
N+3
N+2
tOEoff
tXFLG
tSFA tFAH
FIFOADR
SLCS
Driven
tXFD
tOEon
tRDpwh
tRDpwl tRDpwh
tRDpwl tRDpwh
tRDpwl
tFAH tSFA
N
t=0 T=0
T=1 T=7
T=2 T=3 T=4 T=5 T=6
t=1
t=2 t=3
t=4
NN
SLOE SLRD
FIFO POINTER
N+3
FIFO DATA BUSNot Driven Driven: X N Not Driven
SLOE
N
N+2
N+3
SLRD
N
N+1
SLRD
N+1
SLRD
N+1
N+2
SLRD
N+2
SLRD
N+2
N+1
SLOE
Not Driven
SLOE
N
N+1
N+1
[+] Feedback