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| CY7C68033/CY7C68034 |
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Table 8. |
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56 QFN | Default Pin | NAND | Pin | Default | Description | ||
Pin | Name | Firmware | Type | State | |||
Number | Usage |
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46 | PD1 or |
| CE1# | I/O/Z | I | Multiplexed pin whose function is selected by the IFCONFIG[1:0] | |
| FD[9] |
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| (PD1) | and EPxFIFOCFG.0 (wordwide) bits. |
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| FD[9] is the bidirectional FIFO/GPIF data bus. |
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| CE1# is a NAND chip enable output signal. |
47 | PD2 or | CE2# or GPIO2 | I/O/Z | I | Multiplexed pin whose function is selected by the IFCONFIG[1:0] | ||
| FD[10] |
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| (PD2) | and EPxFIFOCFG.0 (wordwide) bits. |
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| FD[10] is the bidirectional FIFO/GPIF data bus. |
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| CE2# is a NAND chip enable output signal. |
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| GPIO2 is a general purpose I/O signal. |
48 | PD3 or | CE3# or GPIO3 | I/O/Z | I | Multiplexed pin whose function is selected by the IFCONFIG[1:0] | ||
| FD[11] |
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| (PD3) | and EPxFIFOCFG.0 (wordwide) bits. |
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| FD[11] is the bidirectional FIFO/GPIF data bus. |
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| CE3# is a NAND chip enable output signal. |
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| GPIO3 is a general purpose I/O signal. |
49 | PD4 or | CE4# or GPIO4 | I/O/Z | I | Multiplexed pin whose function is selected by the IFCONFIG[1:0] | ||
| FD[12] |
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| (PD4) | and EPxFIFOCFG.0 (wordwide) bits. |
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| FD[12] is the bidirectional FIFO/GPIF data bus. |
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| CE4# is a NAND chip enable output signal. |
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| GPIO4 is a general purpose I/O signal. |
50 | PD5 or | CE5# or GPIO5 | I/O/Z | I | Multiplexed pin whose function is selected by the IFCONFIG[1:0] | ||
| FD[13] |
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| (PD5) | and EPxFIFOCFG.0 (wordwide) bits. |
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| FD[13] is the bidirectional FIFO/GPIF data bus. |
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| CE5# is a NAND chip enable output signal. |
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| GPIO5 is a general purpose I/O signal. |
51 | PD6 or | CE6# or GPIO6 | I/O/Z | I | Multiplexed pin whose function is selected by the IFCONFIG[1:0] | ||
| FD[14] |
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| (PD6) | and EPxFIFOCFG.0 (wordwide) bits. |
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| FD[14] is the bidirectional FIFO/GPIF data bus. |
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| CE6# is a NAND chip enable output signal. |
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| GPIO6 is a general purpose I/O signal. |
52 | PD7 or | CE7# or GPIO7 | I/O/Z | I | Multiplexed pin whose function is selected by the IFCONFIG[1:0] | ||
| FD[15] |
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| (PD7) | and EPxFIFOCFG.0 (wordwide) bits. |
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| FD[15] is the bidirectional FIFO/GPIF data bus. |
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| CE7# is a NAND chip enable output signal. |
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| GPIO7 is a general purpose I/O signal. |
Power and Ground |
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3 | AVCC |
| N/A | Power | N/A | Analog VCC. Connect this pin to 3.3V power source. This signal | |
7 |
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| provides power to the analog section of the chip. |
6 | AGND |
| N/A | Ground | N/A | Analog Ground. Connect to ground with as short a path as | |
10 |
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| possible. |
11 | VCC |
| N/A | Power | N/A | VCC. Connect to 3.3V power source. | |
17 |
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27 |
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32 |
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43 |
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55 |
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12 | GND |
| N/A | Ground | N/A | Ground. | |
26 |
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28 |
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41 |
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53 |
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56 |
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Document #: | Page 17 of 33 |
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