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| CY7C68033/CY7C68034 |
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| Table 8. |
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| 56 QFN | Default Pin | NAND | Pin | Default | Description | ||
| Pin | Name | Firmware | Type | State | |||
| Number | Usage |
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| 39 | PA6 or | GPIO0 | I/O/Z | I | Multiplexed pin whose function is selected by the IFCONFIG[1:0] | ||
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| PKTEND | (Input) |
| (PA6) | bits. | ||
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| PA6 is a bidirectional I/O port pin. |
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| PKTEND is an input used to commit the FIFO packet data to the |
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| endpoint and whose polarity is programmable via FIFOPIN- |
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| POLAR[5]. |
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| GPIO1 is a general purpose I/O signal. |
| 40 | PA7 or | GPIO1 | I/O/Z | I | Multiplexed pin whose function is selected by the IFCONFIG[1:0] | ||
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| FLAGD or | (Input) |
| (PA7) | and PORTACFG[7] bits. | ||
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| SLCS# |
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| PA7 is a bidirectional I/O port pin. |
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| FLAGD is a programmable |
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| SLCS# gates all other slave FIFO enable/strobes |
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| GPIO0 is a general purpose I/O signal. |
| Port B |
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| 18 | PB0 or |
| DD0 | I/O/Z | I | Multiplexed pin whose function is selected by IFCONFIG[1:0]. | |
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| FD[0] |
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| (PB0) | PB0 is a bidirectional I/O port pin. |
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| FD[0] is the bidirectional FIFO/GPIF data bus. |
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| DD0 is a bidirectional NAND data bus signal. |
| 19 | PB1 or |
| DD1 | I/O/Z | I | Multiplexed pin whose function is selected by IFCONFIG[1:0]. | |
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| FD[1] |
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| (PB1) | PB1 is a bidirectional I/O port pin. |
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| FD[1] is the bidirectional FIFO/GPIF data bus. |
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| DD1 is a bidirectional NAND data bus signal. |
| 20 | PB2 or |
| DD2 | I/O/Z | I | Multiplexed pin whose function is selected by IFCONFIG[1:0]. | |
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| FD[2] |
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| (PB2) | PB2 is a bidirectional I/O port pin. |
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| FD[2] is the bidirectional FIFO/GPIF data bus. |
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| DD2 is a bidirectional NAND data bus signal. |
| 21 | PB3 or |
| DD3 | I/O/Z | I | Multiplexed pin whose function is selected by IFCONFIG[1:0]. | |
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| FD[3] |
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| (PB3) | PB3 is a bidirectional I/O port pin. |
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| FD[3] is the bidirectional FIFO/GPIF data bus. |
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| DD3 is a bidirectional NAND data bus signal. |
| 22 | PB4 or |
| DD4 | I/O/Z | I | Multiplexed pin whose function is selected by IFCONFIG[1:0]. | |
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| FD[4] |
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| (PB4) | PB4 is a bidirectional I/O port pin. |
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| FD[4] is the bidirectional FIFO/GPIF data bus. |
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| DD4 is a bidirectional NAND data bus signal. |
| 23 | PB5 or |
| DD5 | I/O/Z | I | Multiplexed pin whose function is selected by IFCONFIG[1:0]. | |
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| FD[5] |
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| (PB5) | PB5 is a bidirectional I/O port pin. |
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| FD[5] is the bidirectional FIFO/GPIF data bus. |
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| DD5 is a bidirectional NAND data bus signal. |
| 24 | PB6 or |
| DD6 | I/O/Z | I | Multiplexed pin whose function is selected by IFCONFIG[1:0]. | |
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| FD[6] |
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| (PB6) | PB6 is a bidirectional I/O port pin. |
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| FD[6] is the bidirectional FIFO/GPIF data bus. |
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| DD6 is a bidirectional NAND data bus signal. |
| 25 | PB7 or |
| DD7 | I/O/Z | I | Multiplexed pin whose function is selected by IFCONFIG[1:0]. | |
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| FD[7] |
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| (PB7) | PB7 is a bidirectional I/O port pin. |
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| FD[7] is the bidirectional FIFO/GPIF data bus. |
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| DD7 is a bidirectional NAND data bus signal. |
| PORT D |
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| 45 | PD0 or |
| CE0# | I/O/Z | I | Multiplexed pin whose function is selected by the IFCONFIG[1:0] | |
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| FD[8] |
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| (PD0) | and EPxFIFOCFG.0 (wordwide) bits. |
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| FD[8] is the bidirectional FIFO/GPIF data bus. |
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| CE0# is a NAND chip enable output signal. |
Document #: |
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| Page 16 of 33 |
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