Cypress CY7C68033, CY7C68034 - page 27

CY7C68033/CY7C68034
Document #: 001-04247 Rev. *D Page 27 of 33
Slave FIFO Asynchronous Packet End Strobe
Figure 13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[9]
Slave FIFO Output Enable
Figure 14. Slave FIFO Output Enable Timing Diagram[13]
Slave FIFO Address to Flags/Data
Figure 15. Slave FIFO Address to Flags/Data Timing Diagram[13]
Table 13.Slave FIFO Asynchronous Packet End Strobe Parameters[15]
Parameter Description Min. Max. Unit
tPEpwl PKTEND Pulse Width LOW 50 ns
tPWpwh PKTEND Pulse Width HIGH 50 ns
tXFLG PKTEND to FLAGS Output Propagation Delay 115 ns
Table 14.Slave FIFO Output Enable Parameters
Parameter Description Min. Max. Unit
tOEon SLOE Assert to FIFO DATA Output 10.5 ns
tOEoff SLOE Deassert to FIFO DATA Hold 10.5 ns
Table 15.Slave FIFO Address to Flags/Data Parameters
Parameter Description Min. Max. Unit
tXFLG FIFOADR[1:0] to FLAGS Output Propagation Delay 10.7 ns
tXFD FIFOADR[1:0] to FIFODATA Output Propagation Delay 14.3 ns
FLAGS
tXFLG
PKTEND tPEpwl
tPEpwh
SLOE
DATA tOEon tOEoff
FIFOADR [1.0]
DATA
tXFLG
tXFD
FLAGS
NN+1
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