Troubleshooting and Repair
range includes a location which when added to sum of the ranges, will produce a known result, such as zero.
Beep codes for system board errors
Table 6-3 (a) BIOS Beep Codes
Beep | Diagnostic | Description | Test Performed |
Code | Code |
|
|
|
|
| |
none | 01h | CPU registers test in | Pattern test of most of the |
|
| progress or failure | registers. Failure will result in a system |
|
|
| halt. |
02h | CMOS write/read test in | Rolling ones test in the shutdown byte | |
|
| progress or failure. | (offset 0Eh) of the CMOS RAM. Failure |
|
|
| will result in a system halt. |
03h | ROM BIOS checksum test in | The range of ROM that includes the | |
|
| progress or failure. | BIOS is checksummed. Failure will result |
|
|
| in a system halt. |
04h | Programmable interval timer | Over a period of time, the current count | |
|
| 0 test in progress or failure. | values in timer 0 are read and |
|
|
| accumulated by ORing them into the |
|
|
| values read so far. It is expected that |
|
|
| during the time period, all bits will be set. |
|
|
| Failure will result in a system halt. |
05h | DMA channel 0 address and | Rolling ones and rolling zeros test of the | |
|
| count register test in progress | address and count registers of DMA |
|
| or failure. | channel 0. Failure will result in a system |
|
|
| halt. |
06h | DMA page register write/read | Pattern test of DMA page registers. | |
|
| test in progress of failure. | Failure will result in a system halt. |
08h | RAM refresh verification test | Over a period of time, the refresh bit (bit | |
|
| in progress or failure. | 4) in port 60h is read and tested. The |
|
|
| refresh bit should toggle from 0 to 1, then |
|
|
| 1 to 0 within the time period. Failure will |
|
|
| result in system halt. |
none | 09h | First 64K RAM test in | No specific test is performed - just |
|
| progress. | indicates that the test is beginning. |
0Ah | First 64K RAM chip or data | The first 64K of RAM is tested with a | |
|
| line failure, | rolling ones test and a pattern test. If any |
|
|
| of the pattern tests fail, then the BIOS |
|
|
| reports that multiple data bits failure. |
|
|
| Failure results in a system halt. |
0Dh | Parity failure first 64K RAM | At the completion of the rolling ones and | |
|
|
| pattern tests of the first 64K, the BIOS |
|
|
| checks the parity error bits (bits 7 and 6) |
|
|
| of port 60h. Failure results in a system |
|
|
| halt. |
FIC A360 Service Manual |