Fujitsu M3097DG Table A.4 Signal delay times definition (1/2)

A.3 Bus Phases

Table A.4 Signal delay times definition (1/2)

No.	Item	Time	Definition
1	Arbitration	2.4 µs	The minimum time an SCSI device shall wait from asserting
	delay		BSY for arbitration until the DATA BUS can be examined to
			see if arbitration has been won. There is no maximum time.
2	Assertion	90 ns	The minimum time that a target shall assert REQ (or REQB)
	period		while using synchronous data transfers. Also, the minimum
			time that an initiator shall assert ACK while using
			synchronous data transfers.
3	Bus Clear	800 ns	The maximum time for an SCSI device to stop driving all bus
	delay		signals after:
			(1) The BUS FREE phase is detected (BSY and SEL both
			false for a bus settle delay)
			(2) SEL is received from another SCSI device during the
			ARBITRATION phase
			(3) The transition of RST to true.
			For the first condition listed, the maximum time for an SCSI
			device to clear the bus is 1200 nanoseconds from BSY and
			SEL first becoming both false. If an SCSI device requires
			more than a bus settle delay to detect BUS FREE phase, it
			shall clear the bus within a bus clear delay minus the excess
			time.
4	Bus free delay	800 ns	The minimum time that an SCSI device shall wait from its
			detection of the BUS FREE phase (BSY and SEL both false
			for a bus settle delay) until its assertion of BSY when going to
			the ARBITRATION phase.
5	Bus set delay	1.8 µs	The maximum time for an SCSI device to assert BSY and its
			SCSI ID bit on the DATA BUS after it detects BUS FREE
			phase (BSY and SEL both false for a bus settle delay) for the
			purpose of entering the ARBITRATION phase
6	Bus settle	400 ns	The minimum time to wait for the bus to settle after changing
	delay		certain control signals as called out in the protocol definitions
7	Cable skew	10 ns	The maximum difference in propagation time allowed
	delay		between any two SCSI bus signals measured between any two
			SCSI devices
8	Data release	400 ns	The maximum time for an initiator to release the DATA BUS
	delay		signals following the transition of the I/O signal from false to
			true
9	Deskew delay	45 ns	The minimum time required for deskew of certain signals

Appendix A-9