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Fujitsu MPB3043AT, MPB3054AT, MPB3032AT, MPB3052AT manual Ultra DMA data burst timing requirements

Models: MPB3043AT MPB3021AT MPB3052AT MPB3032AT MPB3054AT

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5.6.4.2 Ultra DMA data burst timing requirements

Table 5.12 Ultra DMA data burst timing requirements (1 of 2)

NAM	MODE 0		MODE 1		MODE 2			COMMENT
E	(in ns)		(in ns)		(in ns)

	MIN	MAX	MIN	MAX	MIN	MAX

tCYC	114		75		55			Cycle time (from STROBE edge to
								STROBE edge)
t2CYC	235		156		117			Two cycle time (from rising edge to next
								rising edge or from falling edge to next
								falling edge of STROBE)

tDS	15		10		7			Data setup time (at recipient)
tDH	5		5		5			Data hold time (at recipient)
tDVS	70		48		34			Data valid setup time at sender (from data
								bus being valid until STROBE edge)

tDVH	6		6		6			Data valid hold time at sender (from
								STROBE edge until data may become
								invalid)

tFS	0	230	0	200	0	170		First STROBE time (for device to first
								negate DSTROBE from STOP during a
								data in burst)

tLI	0	150	0	150	0	150		Limited interlock time (see Note 1)
tMLI	20		20		20			Interlock time with minimum (see Note 1)
tUI	0		0		0			Unlimited interlock time (see Note 1)
tAZ		10		10		10		Maximum time allowed for output drivers
								to release (from being asserted or
								negated)Minimum delay time required for output
								drivers to assert or negate (from released
tZAH	20		20		20			drivers to assert or negate (from released
tZAH	20		20		20			state)
tZAD	0		0		0			state)



tENV	20	70	20	70	20	70		Envelope time (from DMACK- to STOP
								and HDMARDY- during data in burst
								initiation and from DMACK to STOP
								during data out burst initiation)

tSR		50		30		20		STROBE-to-DMARDY-time (if
								DMARDY- is negated before this long after
								STROBE edge, the recipient shall receive no
								more than one additional data word)

tRFS		75		60		50		Ready-to-final-STROBE time (no
								STROBE edges shall be sent this long
								after negation of DMARDY)

tRP	160		125		100			Ready-to-pause time (that recipient shall
								wait to initiate pause after negating
								DMARDY-)

C141-E045-02EN

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Image 144

Fujitsu MPB3043AT 12 Ultra DMA data burst timing requirements 1 of, negatedMinimum delay time required for output

Contents

MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT DISK DRIVES PRODUCT MANUALC141-E045-02EN Revised contents REVISION RECORDMarch EditionPage DEVICE CONFIGURATION INSTALLATION CONDITIONSPREFACE ChapterConventions for Alert Messages LIABILITY EXCEPTION C141-E045-02ENPage CONTENTS CHAPTERCHAPTER CHAPTERLocation of setting jumpers Factory default settingJumper configuration Circuit ConfigurationCommand block registers Host CommandsCommand code and parameters Command descriptionsDevice pausing an Ultra DMA data out burst Power-on and resetDevice Response to the Reset Response to power-onFIGURES Protocol for command abort WRITE SECTORS command protocolProtocol for the command execution without data transfer Multiword DMA data transfer timing modeTABLES Page 1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.1 Features 1.1.1 Functions and performance1.1.2 Adaptability 1.1.3 Interface5 Error correction and retry by ECC 6 Write cacheC141-E045-02EN 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 Specifications1.3 Power Requirements 1.2.2 Model and product numberTable 1.2 Model names and product numbers Table 1.3 Current and power dissipation Figure 1.1 Current fluctuation Typ. when power is turned on 1.4 Environmental Specifications Environmental specificationsTable 1.5 Acoustic noise specification 1.5 Acoustic NoiseTable 1.6 Shock and vibration specification 1.6 Shock and Vibration1.7 Reliability 1.8 Error Rate 1.9 Media DefectsCHAPTER 2 DEVICE CONFIGURATION 2.1 Device Configuration 2.2 System Configuration2.1 Device Configuration Figure 2.1 Disk drive outerview1 Disk MPB3021AT 1 disk MPB3032AT 2 disks MPB3043AT 2 disksMPB3052AT 3 disks MPB3064AT 3 disks 2 Head C141-E045-02ENFigure 2.2 Configuration of disk media heads MPB3043AT ModelMPB3032ATT Model 2.2 System Configuration 2.2.1 ATA interface Figure 2.3 1 drive system configuration2.2.2 1 drive connection AT busFigure 2.4 2 drives configuration 2.2.3 2 drives connectionHost AT bus Host interface HA Host adaptorPage CHAPTER 3 INSTALLATION CONDITIONS 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings3.1 Dimensions Figure 3.1 Dimensions C141-E045-02EN3.2 Mounting Figure 3.2 OrientationFigure 3.3 Limitation of side-mounting Figure 3.4 Mounting frame structureFigure 3.5 Surface temperature measurement points Table 3.1 Surface temperature measurement points and standard valuesFigure 3.6 Service area 3.3 Cable Connections 3.3.1 Device connector Figure 3.7 Connector locations∙ Power supply connector CN1 ∙ ATA interface connector CN1 Power supply connector CN1 Mode Setting Pins3.3.2 Cable connector specifications Table 3.2 Cable connector specifications3.3.3 Device connection Figure 3.8 Cable connections3.3.4 Power supply connector CN1 Figure 3.9 Power supply connector pins CN1 3.4 Jumper Settings3.4.1 Location of setting jumpers Figure 3.10 Jumper location3.4.2 Factory default setting Figure 3.11 Factory default setting 3.4.3 Jumper configurationFigure 3.12 Jumper setting of master or slave device Figure 3.13 Jumper setting of Cable Select Figure 3.14 Example 1 of Cable SelectFigure 3.15 Example 2 of Cable Select 3 Special setting 1 SP1 a Default modeb Special mode Master Device4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/Write CircuitCHAPTER 4 THEORY OF DEVICE OPERATION 4.7 Servo Control4.2.2 Head MPB 3052AT M odelMPB3064AT Model Figure 4.1 Head structure4.2.3 Spindle 4.2.4 Actuator4.2.5 Air filter 4.3 Circuit Configuration Figure 4.2 MPB30xxAT Block diagram C141-E045-02EN4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5.1 Self-calibration contents 4.5 Self-calibrationTable 4.1 Self-calibration execution timechart 4.5.3 Command processing during self-calibration4.6 Read/write Circuit 4.6.1 Read/write preamplifier PreAMP4.6.2 Write circuit Table 4.2 Write precompensation algorithmFigure 4.4 Read/write circuit block diagram C141-E045-02ENFigure 4.5 Frequency characteristic of programmable filter 4.6.3 Read circuitFigure 4.6 PR4 signal transfer C141-E045-02EN4.6.4 Time base generator circuit Table 4.3 Write clock frequency and transfer rate of each zone 4.7 Servo ControlFigure 4.7 Block diagram of servo control circuit 4.7.1 Servo control circuitFigure 4.8 Physical sector servo configuration on disk surface c. Seek to specified cylinderDrives the VCM to position the head to the specified cylinder d. Calibration5 Power amplifier 2 Servo burst capture circuit3 A/D converter ADC 4 D/A converter DAC4.7.2 Data-surface servo format 4.7.3 Servo frame formatFigure 4.9 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control 2 Acceleration mode 3 Stable rotation modeC141-E045-02EN 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA feature Set 5.6 TimingCHAPTER 5 INTERFACE 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 Interface signals5.1.2 Signal assignment on the connector Table 5.1 Signal assignment on the interface connectorsignal signal This signal is negated to extend the host transfer cycle of any hostregister access Read or Write when the device is not ready to DDMARDY- is a flow control signal for Ultra DMA data out5.2 Logical Interface 5.2.1 I/O registersTable 5.2 I/O registers 5.2.2 Command block registers Diagnostic code X01 No Error Detected X03 Data Buffer Compare Error X05 ROM Sum Check Error X80 Device 1 slave device Failed3 Features register X1F1 4 Sector Count register X1F2The contents of this register indicate the device and the head number Bit 7 Unused Bit 6 L. 0 for CHS mode and 1 for LBA mode Bit 5 UnusedBit 3 HS3 CHS mode head address 3 23. LBA bit Bit 2 HS2 CHS mode head address 3 22. LBA bit9 Status register X1F7 DRDYC141-E045-02EN 10 Command register X1F7 AlwaysAlways C141-E045-02EN5.3 Host Commands 5.2.3 Control block registers5.3.1 Command code and parameters Table 5.3 Command code and parameters 1 ofTable 5.3 Command code and parameters 2 of 5.3.2 Command descriptions At command issuance I/O registers setting contents 1 READ SECTORS X20 or1F7 HCM 1F6 HDHAt command completion I/O registers contents to be read Error information1F7 HST Status informationFigure 5.2 Execution example of READ MULTIPLE command ∙ The data transfer starts at the timing of DMARQ signal assertion In LBA mode1 Single word DMA transfer mode 2 Multiword DMA transfer modeAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents 1F7 HSTAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents 1F7 HSTAt command completion I/O registers contents to be read Error information1F7 HST Status informationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information ∙ The data transfer starts at the timing of DMARQ signal assertion1 Single word DMA transfer mode 2 Multiword DMA transfer mode3 Ultra DMA transfer mode At command issuance I/O registers setting contentsAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information This command can be issued in the LBA modeAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readIn LBA mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error InformationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7HCMTable 5.4 Information to be read by IDENTIFY DEVICE command 1 of C141-E045-02ENTable 5.4 Information to be read by IDENTIFY DEVICE command 2 of Table 5.4 Information to be read by IDENTIFY DEVICE command 3 of At command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 14 SET FEATURES XEFTable 5.5 Features register values and settable modes PIO default transfer mode PIO flow control transfer modeX‘08’ Mode X‘09’ ModeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information Word 59 = 0000 The READ MULTIPLE and WRITE MULTIPLE commands areTable 5.6 Diagnostic code At command issuance I/O registers setting contents At command completion I/O registers contents to be readDiagnostic code 1 This register indicates X‘00’ in the LBA mode 17 FORMAT TRACKAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information This command is operated under the following conditionsAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readPoint of timer Disable of timerAt command issuance I/O registers setting contents Period of timerAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readAt command issuance I/O registers setting contents Period of timerAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information This command is the only way to make the device enter the sleep modeAt command completion I/O registers contents to be read Error information27 CHECK POWER MODE X98 or XE5 The host checks the power mode of the device with this commandAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7 HCMTable 5.7 Features Register values subcommands and functions At command issuance I-O registers setting contents SubcommandAt command completion I-O registers setting contents Error informationTable 5.8 Format of device attribute value data Table 5.9 Format of insurance failure threshold value data Read error rate Seek error ratePower-on time Number of power-on-power-off times∙ Raw attribute value Raw attributes data is retained ∙ Failure prediction capability flagBits 2 to 15 Reserved bits ∙ Check sum ∙ Insurance failure thresholdNOTE - This command may take longer than 30 s to complete At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error information5.3.3 Error posting Table 5.10 Command code and parametersICRC ABRT5.4 Command Protocol 5.4.1 Data transferring commands from device to hostFigure 5.3 Read Sectors command protocol Figure 5.4 Protocol for command abort 5.4.2 Data transferring commands from host to deviceFigure 5.5 WRITE SECTORS command protocol 5.4.3 Commands without data transfer Figure 5.6 Protocol for the command execution without data transfer5.4.4 Other commands 5.4.5 DMA data transfer commandsFigure 5.7 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.2 Phases of operation 5.5.3 Ultra DMA data in commands5.5.3.1 Initiating an Ultra DMA data in burst 5.5.3.3 Pausing an Ultra DMA data in burst 5.5.3.2 The data in transfer5.5.3.4 Terminating an Ultra DMA data in burst b Host terminating an Ultra DMA data in burst C141-E045-02EN5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst5.5.4.3 Pausing an Ultra DMA data out burst 5.5.4.2 The data out transfer5.5.4.4 Terminating an Ultra DMA data out burst b Device terminating an Ultra DMA data out burst C141-E045-02EN5.5.5 Ultra DMA CRC rules 5.5.6 Series termination required for Ultra DMA Table 5.11 Recommended series termination for Ultra DMAFigure 5.8 Ultra DMA termination with pull-up or pull-down 5.6 Timing 5.6.1 PIO data transfer C141-E045-02ENFigure 5.9 PIO data transfer timing 5.6.2 Single word DMA data transfer Figure 5.10 Single word DMA data transfer timingFigure 5.11 Multiword DMA data transfer timing mode 5.6.3 Multiword data transfer5.6.4 Ultra DMA data transfer 5.6.4.1 Initiating an Ultra DMA data in burstFigure 5.12 Initiating an Ultra DMA data in burst 5.6.4.2 Ultra DMA data burst timing requirements Table 5.12 Ultra DMA data burst timing requirements 1 ofnegatedMinimum delay time required for output Table 5.12 Ultra DMA data burst timing requirements 2 of tIORDYZtZIORDY tACK5.6.4.3 Sustained Ultra DMA data in burst Figure 5.13 Sustained Ultra DMA data in burst5.6.4.4 Host pausing an Ultra DMA data in burst Figure 5.14 Host pausing an Ultra DMA data in burst5.6.4.5 Device terminating an Ultra DMA data in burst Figure 5.15 Device terminating an Ultra DMA data in burst5.6.4.6 Host terminating an Ultra DMA data in burst Figure 5.16 Host terminating an Ultra DMA data in burst5.6.4.7 Initiating an Ultra DMA data out burst Figure 5.17 Initiating an Ultra DMA data out burst5.6.4.8 Sustained Ultra DMA data out burst Figure 5.18 Sustained Ultra DMA data out burst5.6.4.9 Device pausing an Ultra DMA data out burst Figure 5.19 Device pausing an Ultra DMA data out burst5.6.4.10 Host terminating an Ultra DMA data out burst Figure 5.20 Host terminating an Ultra DMA data out burst5.6.4.11 Device terminating an Ultra DMA data in burst Figure 5.21 Device terminating an Ultra DMA data out burst5.6.5 Power-on and reset Figure 5.22 Power-on Reset Timing6.1 Device Response to the Reset 6.2 Address Translation 6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache6.6 Write Cache 6.1 Device Response to the Reset CHAPTER 6 OPERATIONS6.1.1 Response to power-on Figure 6.1 Response to power-on6.1.2 Response to hardware reset Figure 6.2 Response to hardware reset6.1.3 Response to software reset Figure 6.3 Response to software reset6.1.4 Response to diagnostic command Figure 6.4 Response to diagnostic command6.2.1 Default parameters Default parameters6.2 Address Translation Figure 6.5 Address translation example in CHS mode 6.2.2 Logical addressFigure 6.6 Address translation example in LBA mode 6.3 Power Save 6.3.1 Power save mode1 Active mode A device enters the active mode under the following conditions∙ Power-on sequence is completed ∙ A command other than power commands is issued6.3.2 Power commands 6.4 Defect Management6.4.1 Spare area 6.4.2 Alternating defective sectorsFigure 6.7 Sector slip processing DefectiveFigure 6.8 Alternate cylinder assignment Sector physicalunused 6.5.1 Data buffer configuration Figure 6.9 Data buffer configuration6.5 Read-Ahead Cache 6.5.2 Caching operation 6.5.3 Usage of read segment 4 Following shows the cache enabled data for next read command Cache enabled dataHAP Segment only for read DAP Stores the read-requested data upto this pointa. Sequential command just after non-sequential command 3 Sequential readMis-hit data Empty dataHAP Read-ahead data DAP Last LBA Start LBA b. Sequential hit HAP Completion of transferring requested dataRead-ahead data Hit datac. Non-sequential read command just after sequential read command HAP Read-ahead data DAP4 Finally, the cache data in the buffer is as follows Read-ahead data Start LBALast position at previous read command DAP Last position at previous read command3 The cache data for next read command is as follows Cache data HAP set to hit position for data transferstopped 6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function I, Place des Etas-Unis, SILIC 310, 94588 Rungis Cedex, FRANCE FUJITSU LIMITED Reader Comment Form