5.6.4.2 Ultra DMA data burst timing requirements
Table 5.12 Ultra DMA data burst timing requirements (1 of 2)
NAM | MODE 0 | MODE 1 | MODE 2 |
| COMMENT | ||||
E | (in ns) | (in ns) | (in ns) |
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| MIN | MAX | MIN | MAX | MIN | MAX |
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tCYC | 114 |
| 75 |
| 55 |
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| Cycle time (from STROBE edge to | |
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| STROBE edge) | |
t2CYC | 235 |
| 156 |
| 117 |
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| Two cycle time (from rising edge to next | |
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| rising edge or from falling edge to next | |
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| falling edge of STROBE) | |
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tDS | 15 |
| 10 |
| 7 |
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| Data setup time (at recipient) | |
tDH | 5 |
| 5 |
| 5 |
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| Data hold time (at recipient) | |
tDVS | 70 |
| 48 |
| 34 |
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| Data valid setup time at sender (from data | |
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| bus being valid until STROBE edge) | |
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tDVH | 6 |
| 6 |
| 6 |
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| Data valid hold time at sender (from | |
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| STROBE edge until data may become | |
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| invalid) | |
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tFS | 0 | 230 | 0 | 200 | 0 | 170 |
| First STROBE time (for device to first | |
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| negate DSTROBE from STOP during a | |
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| data in burst) | |
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tLI | 0 | 150 | 0 | 150 | 0 | 150 |
| Limited interlock time (see Note 1) | |
tMLI | 20 |
| 20 |
| 20 |
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| Interlock time with minimum (see Note 1) | |
tUI | 0 |
| 0 |
| 0 |
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| Unlimited interlock time (see Note 1) | |
tAZ |
| 10 |
| 10 |
| 10 |
| Maximum time allowed for output drivers | |
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| to release (from being asserted or | |
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| negated)Minimum delay time required for output |
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| drivers to assert or negate (from released |
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tZAH | 20 |
| 20 |
| 20 |
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| state) |
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tZAD | 0 |
| 0 |
| 0 |
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tENV | 20 | 70 | 20 | 70 | 20 | 70 |
| Envelope time (from DMACK- to STOP | |
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| and HDMARDY- during data in burst | |
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| initiation and from DMACK to STOP | |
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| during data out burst initiation) | |
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tSR |
| 50 |
| 30 |
| 20 |
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| DMARDY- is negated before this long after | |
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| STROBE edge, the recipient shall receive no | |
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| more than one additional data word) | |
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tRFS |
| 75 |
| 60 |
| 50 |
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| STROBE edges shall be sent this long | |
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| after negation of DMARDY) | |
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tRP | 160 |
| 125 |
| 100 |
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| wait to initiate pause after negating | |
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5 - 79 |
