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Fujitsu MPB3043AT, MPB3054AT, MPB3032AT, MPB3052AT Timing 5.6.1 PIO data transfer, C141-E045-02EN

Models: MPB3043AT MPB3021AT MPB3052AT MPB3032AT MPB3054AT

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5.6Timing

5.6.1PIO data transfer

Figure 5.9 shows of the data transfer timing between the device and the host system.

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C141-E045-02EN

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Fujitsu MPB3043AT, MPB3054AT, MPB3032AT, MPB3052AT, MPB3021AT manual Timing 5.6.1 PIO data transfer, C141-E045-02EN

Contents

PRODUCT MANUAL MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT DISK DRIVESC141-E045-02EN Edition Revised contentsREVISION RECORD MarchPage Chapter DEVICE CONFIGURATIONINSTALLATION CONDITIONS PREFACEConventions for Alert Messages C141-E045-02EN LIABILITY EXCEPTIONPage CHAPTER CONTENTSCHAPTER CHAPTERCircuit Configuration Location of setting jumpersFactory default setting Jumper configurationCommand descriptions Command block registersHost Commands Command code and parametersResponse to power-on Device pausing an Ultra DMA data out burstPower-on and reset Device Response to the ResetFIGURES Host pausing an Ultra DMA data in burst Protocol for command abortWRITE SECTORS command protocol Protocol for the command execution without data transferTABLES Page 1.1 Features 1.1.1 Functions and performance 1.1 Features 1.2 Device Specifications 1.3 Power Requirements1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate1.1.3 Interface 1.1.2 Adaptability6 Write cache 5 Error correction and retry by ECCC141-E045-02EN Table 1.1 Specifications 1.2 Device Specifications 1.2.1 Specifications summary1.2.2 Model and product number 1.3 Power RequirementsTable 1.2 Model names and product numbers Table 1.3 Current and power dissipation Figure 1.1 Current fluctuation Typ. when power is turned on 1.5 Acoustic Noise 1.4 Environmental SpecificationsEnvironmental specifications Table 1.5 Acoustic noise specification1.6 Shock and Vibration Table 1.6 Shock and vibration specification1.7 Reliability 1.9 Media Defects 1.8 Error RateFigure 2.1 Disk drive outerview CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration 2.2 System Configuration 2.1 Device ConfigurationC141-E045-02EN 1 DiskMPB3021AT 1 disk MPB3032AT 2 disks MPB3043AT 2 disks MPB3052AT 3 disks MPB3064AT 3 disks 2 HeadMPB3043AT Model Figure 2.2 Configuration of disk media headsMPB3032ATT Model AT bus 2.2 System Configuration 2.2.1 ATA interfaceFigure 2.3 1 drive system configuration 2.2.2 1 drive connectionHA Host adaptor Figure 2.4 2 drives configuration2.2.3 2 drives connection Host AT bus Host interfacePage 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings CHAPTER 3 INSTALLATION CONDITIONS3.1 Dimensions C141-E045-02EN Figure 3.1 DimensionsFigure 3.2 Orientation 3.2 MountingFigure 3.4 Mounting frame structure Figure 3.3 Limitation of side-mountingTable 3.1 Surface temperature measurement points and standard values Figure 3.5 Surface temperature measurement pointsFigure 3.6 Service area Power supply connector CN1 Mode Setting Pins 3.3 Cable Connections 3.3.1 Device connectorFigure 3.7 Connector locations ∙ Power supply connector CN1 ∙ ATA interface connector CN1Figure 3.8 Cable connections 3.3.2 Cable connector specificationsTable 3.2 Cable connector specifications 3.3.3 Device connectionFigure 3.10 Jumper location 3.3.4 Power supply connector CN1Figure 3.9 Power supply connector pins CN1 3.4 Jumper Settings 3.4.1 Location of setting jumpersFigure 3.11 Factory default setting 3.4.3 Jumper configuration 3.4.2 Factory default settingFigure 3.12 Jumper setting of master or slave device Figure 3.14 Example 1 of Cable Select Figure 3.13 Jumper setting of Cable SelectFigure 3.15 Example 2 of Cable Select Slave Device 3 Special setting 1 SP1a Default mode Master Device4.7 Servo Control 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/Write Circuit CHAPTER 4 THEORY OF DEVICE OPERATIONFigure 4.1 Head structure 4.2.2 HeadMPB 3052AT M odel MPB3064AT Model4.2.4 Actuator 4.2.3 Spindle4.2.5 Air filter 4.3 Circuit Configuration C141-E045-02EN Figure 4.2 MPB30xxAT Block diagram4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5 Self-calibration 4.5.1 Self-calibration contents4.5.3 Command processing during self-calibration Table 4.1 Self-calibration execution timechartTable 4.2 Write precompensation algorithm 4.6 Read/write Circuit4.6.1 Read/write preamplifier PreAMP 4.6.2 Write circuitC141-E045-02EN Figure 4.4 Read/write circuit block diagram4.6.3 Read circuit Figure 4.5 Frequency characteristic of programmable filterC141-E045-02EN Figure 4.6 PR4 signal transfer4.6.4 Time base generator circuit 4.7 Servo Control Table 4.3 Write clock frequency and transfer rate of each zone4.7.1 Servo control circuit Figure 4.7 Block diagram of servo control circuitd. Calibration Figure 4.8 Physical sector servo configuration on disk surfacec. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder4 D/A converter DAC 5 Power amplifier2 Servo burst capture circuit 3 A/D converter ADC4.7.3 Servo frame format 4.7.2 Data-surface servo formatFigure 4.9 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control 3 Stable rotation mode 2 Acceleration modeC141-E045-02EN 5.4 Command Protocol 5.5 Ultra DMA feature Set 5.6 Timing 5.1 Physical Interface 5.2 Logical Interface 5.3 Host CommandsCHAPTER 5 INTERFACE Figure 5.1 Interface signals 5.1 Physical Interface 5.1.1 Interface signalsTable 5.1 Signal assignment on the interface connector 5.1.2 Signal assignment on the connectorsignal DDMARDY- is a flow control signal for Ultra DMA data out signalThis signal is negated to extend the host transfer cycle of any host register access Read or Write when the device is not ready to5.2.1 I/O registers 5.2 Logical InterfaceTable 5.2 I/O registers 5.2.2 Command block registers 4 Sector Count register X1F2 Diagnostic code X01 No Error Detected X03 Data Buffer Compare ErrorX05 ROM Sum Check Error X80 Device 1 slave device Failed 3 Features register X1F17 Cylinder High register X1F5 The contents of this register indicate the device and the head number6 Cylinder Low register X1F4 Under the LBA mode, this register indicates LBA bits 15 toDRDY 9 Status register X1F7C141-E045-02EN C141-E045-02EN 10 Command register X1F7Always Always5.2.3 Control block registers 5.3 Host CommandsTable 5.3 Command code and parameters 1 of 5.3.1 Command code and parametersTable 5.3 Command code and parameters 2 of 5.3.2 Command descriptions 1F6 HDH At command issuance I/O registers setting contents1 READ SECTORS X20 or 1F7 HCMStatus information At command completion I/O registers contents to be readError information 1F7 HSTFigure 5.2 Execution example of READ MULTIPLE command In LBA mode ∙ The data transfer starts at the timing of DMARQ signal assertionAt command issuance I/O registers setting contents 3 READ DMA XC8 or XC91F7 HST At command completion I/O registers contents to be readError information At command issuance I/O registers setting contents1F7 HST At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsStatus information At command completion I/O registers contents to be readError information 1F7 HST∙ The data transfer starts at the timing of DMARQ signal assertion At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error information1 Single word DMA transfer mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationThis command can be issued in the LBA mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAt command completion I/O registers contents to be read At command completion I/O registers contents to be readError information At command issuance I/O registers setting contents11 INITIALIZE DEVICE PARAMETERS At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error Information1F7HCM At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationC141-E045-02EN Table 5.4 Information to be read by IDENTIFY DEVICE command 1 ofTable 5.4 Information to be read by IDENTIFY DEVICE command 2 of Table 5.4 Information to be read by IDENTIFY DEVICE command 3 of 14 SET FEATURES XEF At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationTable 5.5 Features register values and settable modes PIO flow control transfer mode PIO default transfer mode00000 X‘00’Word 59 = 0000 The READ MULTIPLE and WRITE MULTIPLE commands are At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationTable 5.6 Diagnostic code The READ LONG command supports only single sector operation At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Diagnostic codeThis command is operated under the following conditions At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAt command completion I/O registers contents to be read At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsPeriod of timer Point of timerDisable of timer At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsError information At command issuance I/O registers setting contentsPeriod of timer At command completion I/O registers contents to be readThis command is the only way to make the device enter the sleep mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationThe host checks the power mode of the device with this command At command completion I/O registers contents to be readError information 27 CHECK POWER MODE X98 or XE51F7 HCM At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationTable 5.7 Features Register values subcommands and functions Error information At command issuance I-O registers setting contentsSubcommand At command completion I-O registers setting contentsTable 5.8 Format of device attribute value data Table 5.9 Format of insurance failure threshold value data Number of power-on-power-off times Read error rateSeek error rate Power-on time∙ Insurance failure threshold ∙ Raw attribute value Raw attributes data is retained∙ Failure prediction capability flag Bits 2 to 15 Reserved bits ∙ Check sumError information NOTE - This command may take longer than 30 s to completeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readABRT 5.3.3 Error postingTable 5.10 Command code and parameters ICRC5.4.1 Data transferring commands from device to host 5.4 Command ProtocolFigure 5.3 Read Sectors command protocol 5.4.2 Data transferring commands from host to device Figure 5.4 Protocol for command abortFigure 5.5 WRITE SECTORS command protocol Figure 5.6 Protocol for the command execution without data transfer 5.4.3 Commands without data transfer5.4.5 DMA data transfer commands 5.4.4 Other commandsFigure 5.7 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.3 Ultra DMA data in commands 5.5.2 Phases of operation5.5.3.1 Initiating an Ultra DMA data in burst 5.5.3.2 The data in transfer 5.5.3.3 Pausing an Ultra DMA data in burst5.5.3.4 Terminating an Ultra DMA data in burst C141-E045-02EN b Host terminating an Ultra DMA data in burst5.5.4.1 Initiating an Ultra DMA data out burst 5.5.4 Ultra DMA data out commands5.5.4.2 The data out transfer 5.5.4.3 Pausing an Ultra DMA data out burst5.5.4.4 Terminating an Ultra DMA data out burst C141-E045-02EN b Device terminating an Ultra DMA data out burst5.5.5 Ultra DMA CRC rules Table 5.11 Recommended series termination for Ultra DMA 5.5.6 Series termination required for Ultra DMAFigure 5.8 Ultra DMA termination with pull-up or pull-down C141-E045-02EN 5.6 Timing 5.6.1 PIO data transferFigure 5.9 PIO data transfer timing Figure 5.10 Single word DMA data transfer timing 5.6.2 Single word DMA data transferFigure 5.11 Multiword DMA data transfer timing mode 5.6.3 Multiword data transfer5.6.4.1 Initiating an Ultra DMA data in burst 5.6.4 Ultra DMA data transferFigure 5.12 Initiating an Ultra DMA data in burst Table 5.12 Ultra DMA data burst timing requirements 1 of 5.6.4.2 Ultra DMA data burst timing requirementsnegatedMinimum delay time required for output tACK Table 5.12 Ultra DMA data burst timing requirements 2 oftIORDYZ tZIORDYFigure 5.13 Sustained Ultra DMA data in burst 5.6.4.3 Sustained Ultra DMA data in burstFigure 5.14 Host pausing an Ultra DMA data in burst 5.6.4.4 Host pausing an Ultra DMA data in burstFigure 5.15 Device terminating an Ultra DMA data in burst 5.6.4.5 Device terminating an Ultra DMA data in burstFigure 5.16 Host terminating an Ultra DMA data in burst 5.6.4.6 Host terminating an Ultra DMA data in burstFigure 5.17 Initiating an Ultra DMA data out burst 5.6.4.7 Initiating an Ultra DMA data out burstFigure 5.18 Sustained Ultra DMA data out burst 5.6.4.8 Sustained Ultra DMA data out burstFigure 5.19 Device pausing an Ultra DMA data out burst 5.6.4.9 Device pausing an Ultra DMA data out burstFigure 5.20 Host terminating an Ultra DMA data out burst 5.6.4.10 Host terminating an Ultra DMA data out burstFigure 5.21 Device terminating an Ultra DMA data out burst 5.6.4.11 Device terminating an Ultra DMA data in burstFigure 5.22 Power-on Reset Timing 5.6.5 Power-on and resetCHAPTER 6 OPERATIONS 6.1 Device Response to the Reset 6.2 Address Translation6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache 6.1 Device Response to the ResetFigure 6.1 Response to power-on 6.1.1 Response to power-onFigure 6.2 Response to hardware reset 6.1.2 Response to hardware resetFigure 6.3 Response to software reset 6.1.3 Response to software resetFigure 6.4 Response to diagnostic command 6.1.4 Response to diagnostic commandDefault parameters 6.2.1 Default parameters6.2 Address Translation Figure 6.5 Address translation example in CHS mode 6.2.2 Logical address6.3.1 Power save mode Figure 6.6 Address translation example in LBA mode 6.3 Power Save∙ After completion of power-on sequence ∙ Power-on sequence is completed∙ A command other than power commands is issued ∙ Reset hardware or software 2 Idle mode6.4 Defect Management 6.3.2 Power commandsDefective 6.4.1 Spare area6.4.2 Alternating defective sectors Figure 6.7 Sector slip processingSector physical Figure 6.8 Alternate cylinder assignmentunused Figure 6.9 Data buffer configuration 6.5.1 Data buffer configuration6.5 Read-Ahead Cache 6.5.2 Caching operation 6.5.3 Usage of read segment Stores the read-requested data upto this point 4 Following shows the cache enabled data for next read commandCache enabled data HAP Segment only for read DAPEmpty data a. Sequential command just after non-sequential command3 Sequential read Mis-hit dataHit data HAP Read-ahead data DAP Last LBA Start LBA b. Sequential hitHAP Completion of transferring requested data Read-ahead dataStart LBA c. Non-sequential read command just after sequential read commandHAP Read-ahead data DAP 4 Finally, the cache data in the buffer is as follows Read-ahead dataHAP set to hit position for data transfer Last position at previous read commandDAP Last position at previous read command 3 The cache data for next read command is as follows Cache datastopped 6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function I, Place des Etas-Unis, SILIC 310, 94588 Rungis Cedex, FRANCE Reader Comment Form FUJITSU LIMITED