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Fujitsu MPB3032AT, MPB3054AT, MPB3052AT, MPB3021AT manual Address Translation, Default parameters

Models: MPB3043AT MPB3021AT MPB3052AT MPB3032AT MPB3054AT

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6.2Address Translation

When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation).

Following subsections explains the CHS translation mode.

6.2.1Default parameters

In the logical to physical address translation, the logical cylinder, head, and sector addresses are translated to the physical cylinder, head, and sector addresses based on the number of heads and the number of sectors per track which are specified with an INITIALIZE DEVICE PARAMETERS command. This is called as the current translation mode.

If the number of heads and the number of sectors are not specified with an INITIALIZE DEVICE PARAMETERS command, the default values listed in Table 6.1 are used. This is called as the default translation mode. The parameters in Table 6.1 are called BIOS specification.

		Table 6.1	Default parameters

		MPB		MPB	MPB	MPB	MPB
		3064AT		3052AT	3043AT	3032AT	3021AT

	Number of cylinders	13,410		10,850	8,940	6,704	4,470
Parameters
Parameters	Number of head	15
(logical)	Number of head	15
(logical)
	Number of	63
	sectors/track

Formatted capacity (MB)		6,488.2		5,249.6	4,325.5	3,343.6	2,162.7

As long as the formatted capacity of the IDD does not exceed the value shown on Table 6.1, the host can freely specify the number of cylinders, heads, and sectors per track.

Generally, the device recognizes the number of heads and sectors per track with the INITIALIZE DEVICE PARAMETER command. However, it cannot recognizes the number of cylinders. In other words, there is no way for the device to recognize a host access area on logical cylinders. Thus the host should manage cylinder access to the device.

The host can specify a logical address freely within an area where an address can be specified (within the specified number of cylinders, heads, and sectors per track) in the current translation mode.

The host can read an addressable parameter information from the device by the IDENTIFY DEVICE command (Words 54 to 56).

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C141-E045-02EN

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Fujitsu MPB3032AT, MPB3054AT, MPB3052AT, MPB3021AT, MPB3043AT manual Address Translation, Default parameters

Contents

C141-E045-02EN MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT DISK DRIVESPRODUCT MANUAL REVISION RECORD Revised contentsMarch EditionPage INSTALLATION CONDITIONS DEVICE CONFIGURATIONPREFACE ChapterConventions for Alert Messages C141-E045-02EN LIABILITY EXCEPTIONPage CHAPTER CONTENTSCHAPTER CHAPTERFactory default setting Location of setting jumpersJumper configuration Circuit ConfigurationHost Commands Command block registersCommand code and parameters Command descriptionsPower-on and reset Device pausing an Ultra DMA data out burstDevice Response to the Reset Response to power-onFIGURES WRITE SECTORS command protocol Protocol for command abortProtocol for the command execution without data transfer Multiword DMA data transfer timing modeTABLES Page 1.4 Environmental Specifications 1.5 Acoustic Noise 1.1 Features 1.2 Device Specifications 1.3 Power Requirements1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.1 Features 1.1.1 Functions and performance1.1.3 Interface 1.1.2 AdaptabilityC141-E045-02EN 5 Error correction and retry by ECC6 Write cache Table 1.1 Specifications 1.2 Device Specifications 1.2.1 Specifications summaryTable 1.2 Model names and product numbers 1.3 Power Requirements1.2.2 Model and product number Table 1.3 Current and power dissipation Figure 1.1 Current fluctuation Typ. when power is turned on Environmental specifications 1.4 Environmental SpecificationsTable 1.5 Acoustic noise specification 1.5 Acoustic Noise1.7 Reliability Table 1.6 Shock and vibration specification1.6 Shock and Vibration 1.9 Media Defects 1.8 Error Rate2.1 Device Configuration 2.2 System Configuration CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration Figure 2.1 Disk drive outerviewMPB3021AT 1 disk MPB3032AT 2 disks MPB3043AT 2 disks 1 DiskMPB3052AT 3 disks MPB3064AT 3 disks 2 Head C141-E045-02ENMPB3032ATT Model Figure 2.2 Configuration of disk media headsMPB3043AT Model Figure 2.3 1 drive system configuration 2.2 System Configuration 2.2.1 ATA interface2.2.2 1 drive connection AT bus2.2.3 2 drives connection Figure 2.4 2 drives configurationHost AT bus Host interface HA Host adaptorPage 3.1 Dimensions CHAPTER 3 INSTALLATION CONDITIONS3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings C141-E045-02EN Figure 3.1 DimensionsFigure 3.2 Orientation 3.2 MountingFigure 3.4 Mounting frame structure Figure 3.3 Limitation of side-mountingTable 3.1 Surface temperature measurement points and standard values Figure 3.5 Surface temperature measurement pointsFigure 3.6 Service area Figure 3.7 Connector locations 3.3 Cable Connections 3.3.1 Device connector∙ Power supply connector CN1 ∙ ATA interface connector CN1 Power supply connector CN1 Mode Setting PinsTable 3.2 Cable connector specifications 3.3.2 Cable connector specifications3.3.3 Device connection Figure 3.8 Cable connectionsFigure 3.9 Power supply connector pins CN1 3.4 Jumper Settings 3.3.4 Power supply connector CN13.4.1 Location of setting jumpers Figure 3.10 Jumper locationFigure 3.12 Jumper setting of master or slave device 3.4.2 Factory default settingFigure 3.11 Factory default setting 3.4.3 Jumper configuration Figure 3.15 Example 2 of Cable Select Figure 3.13 Jumper setting of Cable SelectFigure 3.14 Example 1 of Cable Select a Default mode 3 Special setting 1 SP1b Special mode Master Device4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/Write Circuit 4.1 Outline 4.2 Subassemblies 4.3 Circuit ConfigurationCHAPTER 4 THEORY OF DEVICE OPERATION 4.7 Servo ControlMPB 3052AT M odel 4.2.2 HeadMPB3064AT Model Figure 4.1 Head structure4.2.5 Air filter 4.2.3 Spindle4.2.4 Actuator 4.3 Circuit Configuration C141-E045-02EN Figure 4.2 MPB30xxAT Block diagram4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5 Self-calibration 4.5.1 Self-calibration contents4.5.3 Command processing during self-calibration Table 4.1 Self-calibration execution timechart4.6.1 Read/write preamplifier PreAMP 4.6 Read/write Circuit4.6.2 Write circuit Table 4.2 Write precompensation algorithmC141-E045-02EN Figure 4.4 Read/write circuit block diagram4.6.3 Read circuit Figure 4.5 Frequency characteristic of programmable filterC141-E045-02EN Figure 4.6 PR4 signal transfer4.6.4 Time base generator circuit 4.7 Servo Control Table 4.3 Write clock frequency and transfer rate of each zone4.7.1 Servo control circuit Figure 4.7 Block diagram of servo control circuitc. Seek to specified cylinder Figure 4.8 Physical sector servo configuration on disk surfaceDrives the VCM to position the head to the specified cylinder d. Calibration2 Servo burst capture circuit 5 Power amplifier3 A/D converter ADC 4 D/A converter DACFigure 4.9 Servo frame format 4.7.2 Data-surface servo format4.7.3 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control C141-E045-02EN 2 Acceleration mode3 Stable rotation mode CHAPTER 5 INTERFACE 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands5.4 Command Protocol 5.5 Ultra DMA feature Set 5.6 Timing Figure 5.1 Interface signals 5.1 Physical Interface 5.1.1 Interface signalsTable 5.1 Signal assignment on the interface connector 5.1.2 Signal assignment on the connectorsignal This signal is negated to extend the host transfer cycle of any host signalregister access Read or Write when the device is not ready to DDMARDY- is a flow control signal for Ultra DMA data out5.2.1 I/O registers 5.2 Logical InterfaceTable 5.2 I/O registers 5.2.2 Command block registers X05 ROM Sum Check Error X80 Device 1 slave device Failed Diagnostic code X01 No Error Detected X03 Data Buffer Compare Error3 Features register X1F1 4 Sector Count register X1F2Bit 7 Unused Bit 6 L. 0 for CHS mode and 1 for LBA mode Bit 5 Unused The contents of this register indicate the device and the head numberBit 3 HS3 CHS mode head address 3 23. LBA bit Bit 2 HS2 CHS mode head address 3 22. LBA bitC141-E045-02EN 9 Status register X1F7DRDY Always 10 Command register X1F7Always C141-E045-02EN5.2.3 Control block registers 5.3 Host CommandsTable 5.3 Command code and parameters 1 of 5.3.1 Command code and parametersTable 5.3 Command code and parameters 2 of 5.3.2 Command descriptions 1 READ SECTORS X20 or At command issuance I/O registers setting contents1F7 HCM 1F6 HDHError information At command completion I/O registers contents to be read1F7 HST Status informationFigure 5.2 Execution example of READ MULTIPLE command In LBA mode ∙ The data transfer starts at the timing of DMARQ signal assertion1 Single word DMA transfer mode 2 Multiword DMA transfer modeError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents 1F7 HSTError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents 1F7 HSTError information At command completion I/O registers contents to be read1F7 HST Status informationAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information ∙ The data transfer starts at the timing of DMARQ signal assertion2 Multiword DMA transfer mode 1 Single word DMA transfer mode3 Ultra DMA transfer mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information This command can be issued in the LBA modeError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents At command completion I/O registers contents to be readAt command issuance I/O registers setting contents In LBA modeAt command completion I/O registers contents to be read Error InformationAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information 1F7HCMC141-E045-02EN Table 5.4 Information to be read by IDENTIFY DEVICE command 1 ofTable 5.4 Information to be read by IDENTIFY DEVICE command 2 of Table 5.4 Information to be read by IDENTIFY DEVICE command 3 of At command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information 14 SET FEATURES XEFTable 5.5 Features register values and settable modes PIO flow control transfer mode PIO default transfer modeX‘08’ Mode X‘09’ ModeAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information Word 59 = 0000 The READ MULTIPLE and WRITE MULTIPLE commands areTable 5.6 Diagnostic code At command completion I/O registers contents to be read At command issuance I/O registers setting contentsDiagnostic code 1 This register indicates X‘00’ in the LBA mode 17 FORMAT TRACKAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information This command is operated under the following conditionsAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information At command issuance I/O registers setting contentsError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents At command completion I/O registers contents to be readDisable of timer Point of timerAt command issuance I/O registers setting contents Period of timerError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents At command completion I/O registers contents to be readPeriod of timer At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information This command is the only way to make the device enter the sleep modeError information At command completion I/O registers contents to be read27 CHECK POWER MODE X98 or XE5 The host checks the power mode of the device with this commandAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsError information 1F7 HCMTable 5.7 Features Register values subcommands and functions Subcommand At command issuance I-O registers setting contentsAt command completion I-O registers setting contents Error informationTable 5.8 Format of device attribute value data Table 5.9 Format of insurance failure threshold value data Seek error rate Read error ratePower-on time Number of power-on-power-off times∙ Failure prediction capability flag ∙ Raw attribute value Raw attributes data is retainedBits 2 to 15 Reserved bits ∙ Check sum ∙ Insurance failure thresholdAt command issuance I/O registers setting contents NOTE - This command may take longer than 30 s to completeAt command completion I/O registers contents to be read Error informationTable 5.10 Command code and parameters 5.3.3 Error postingICRC ABRT5.4.1 Data transferring commands from device to host 5.4 Command ProtocolFigure 5.3 Read Sectors command protocol 5.4.2 Data transferring commands from host to device Figure 5.4 Protocol for command abortFigure 5.5 WRITE SECTORS command protocol Figure 5.6 Protocol for the command execution without data transfer 5.4.3 Commands without data transfer5.4.5 DMA data transfer commands 5.4.4 Other commandsFigure 5.7 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.3.1 Initiating an Ultra DMA data in burst 5.5.2 Phases of operation5.5.3 Ultra DMA data in commands 5.5.3.2 The data in transfer 5.5.3.3 Pausing an Ultra DMA data in burst5.5.3.4 Terminating an Ultra DMA data in burst C141-E045-02EN b Host terminating an Ultra DMA data in burst5.5.4.1 Initiating an Ultra DMA data out burst 5.5.4 Ultra DMA data out commands5.5.4.2 The data out transfer 5.5.4.3 Pausing an Ultra DMA data out burst5.5.4.4 Terminating an Ultra DMA data out burst C141-E045-02EN b Device terminating an Ultra DMA data out burst5.5.5 Ultra DMA CRC rules Figure 5.8 Ultra DMA termination with pull-up or pull-down 5.5.6 Series termination required for Ultra DMATable 5.11 Recommended series termination for Ultra DMA C141-E045-02EN 5.6 Timing 5.6.1 PIO data transferFigure 5.9 PIO data transfer timing Figure 5.10 Single word DMA data transfer timing 5.6.2 Single word DMA data transfer5.6.3 Multiword data transfer Figure 5.11 Multiword DMA data transfer timing modeFigure 5.12 Initiating an Ultra DMA data in burst 5.6.4 Ultra DMA data transfer5.6.4.1 Initiating an Ultra DMA data in burst negatedMinimum delay time required for output 5.6.4.2 Ultra DMA data burst timing requirementsTable 5.12 Ultra DMA data burst timing requirements 1 of tIORDYZ Table 5.12 Ultra DMA data burst timing requirements 2 oftZIORDY tACKFigure 5.13 Sustained Ultra DMA data in burst 5.6.4.3 Sustained Ultra DMA data in burstFigure 5.14 Host pausing an Ultra DMA data in burst 5.6.4.4 Host pausing an Ultra DMA data in burstFigure 5.15 Device terminating an Ultra DMA data in burst 5.6.4.5 Device terminating an Ultra DMA data in burstFigure 5.16 Host terminating an Ultra DMA data in burst 5.6.4.6 Host terminating an Ultra DMA data in burstFigure 5.17 Initiating an Ultra DMA data out burst 5.6.4.7 Initiating an Ultra DMA data out burstFigure 5.18 Sustained Ultra DMA data out burst 5.6.4.8 Sustained Ultra DMA data out burstFigure 5.19 Device pausing an Ultra DMA data out burst 5.6.4.9 Device pausing an Ultra DMA data out burstFigure 5.20 Host terminating an Ultra DMA data out burst 5.6.4.10 Host terminating an Ultra DMA data out burstFigure 5.21 Device terminating an Ultra DMA data out burst 5.6.4.11 Device terminating an Ultra DMA data in burstFigure 5.22 Power-on Reset Timing 5.6.5 Power-on and reset6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.1 Device Response to the Reset 6.2 Address Translation6.6 Write Cache 6.1 Device Response to the Reset CHAPTER 6 OPERATIONSFigure 6.1 Response to power-on 6.1.1 Response to power-onFigure 6.2 Response to hardware reset 6.1.2 Response to hardware resetFigure 6.3 Response to software reset 6.1.3 Response to software resetFigure 6.4 Response to diagnostic command 6.1.4 Response to diagnostic command6.2 Address Translation 6.2.1 Default parametersDefault parameters 6.2.2 Logical address Figure 6.5 Address translation example in CHS mode6.3.1 Power save mode Figure 6.6 Address translation example in LBA mode 6.3 Power SaveA device enters the active mode under the following conditions 1 Active mode∙ Power-on sequence is completed ∙ A command other than power commands is issued6.4 Defect Management 6.3.2 Power commands6.4.2 Alternating defective sectors 6.4.1 Spare areaFigure 6.7 Sector slip processing Defectiveunused Figure 6.8 Alternate cylinder assignmentSector physical 6.5 Read-Ahead Cache 6.5.1 Data buffer configurationFigure 6.9 Data buffer configuration 6.5.2 Caching operation 6.5.3 Usage of read segment Cache enabled data 4 Following shows the cache enabled data for next read commandHAP Segment only for read DAP Stores the read-requested data upto this point3 Sequential read a. Sequential command just after non-sequential commandMis-hit data Empty dataHAP Completion of transferring requested data HAP Read-ahead data DAP Last LBA Start LBA b. Sequential hitRead-ahead data Hit dataHAP Read-ahead data DAP c. Non-sequential read command just after sequential read command4 Finally, the cache data in the buffer is as follows Read-ahead data Start LBADAP Last position at previous read command Last position at previous read command3 The cache data for next read command is as follows Cache data HAP set to hit position for data transferstopped 6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function I, Place des Etas-Unis, SILIC 310, 94588 Rungis Cedex, FRANCE Reader Comment Form FUJITSU LIMITED