Logical Interface, 1 I/O registers | Fujitsu MPB3032AT, MPB3054AT

5.2Logical Interface

The device can operate for command execution in either address-specified mode; cylinder- head-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No. under the LBA mode, and all bits of the Cylinder High, Cylinder Low, and Sector Number registers are LBA bits.

The sector No. under the LBA mode proceeds in the ascending order with the start point of LBA0 (defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command, the sector LBA address is not changed.

LBA = [((Cylinder No.) × (Number of head) + (Head No.)) × (Number of sector/track)]

+(Sector No.) – 1

5.2.1I/O registers

Communication between the host system and the device is done through input-output (I/O) registers of the device.

These I/O registers can be selected by the coded signals, CS0–, CS1–, and DA0 to DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers.

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C141-E045-02EN

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Fujitsu MPB3032AT, MPB3054AT, MPB3052AT, MPB3021AT, MPB3043AT manual Logical Interface, 1 I/O registers

Contents

C141-E045-02EN Revision Record Page Chapter Preface Conventions for Alert Messages Liability Exception Page Contents Interface Theory of Device OperationPage Operations Figures Page Tables Page Device Overview Features Functions and performance Interface AdaptabilityPage Specifications Device Specifications Specifications summary Model names and product numbers Model and product number Current and power dissipation Current fluctuation Typ. when power is turned on Acoustic noise specification Shock and vibration specification Error Rate Disk drive outerview Device Configuration System ConfigurationPage MPB3043AT Model Configuration of disk media heads 2 1 drive connection System Configuration ATA interface 3 2 drives connection 2 drives configurationPage Dimensions Mounting Cable Connections Jumper Settings Installation Conditions Dimensions Orientation PCA Limitation of side-mountingPage Service area ATA Cable Connections Device connector Device connection Cable connector specificationsSpecters Strip AMP CN1 Power supply connector CN1+12V Return +5V Return 11 Factory default setting Jumper configuration Factory default setting 14 Example 1 of Cable Select 13 Jumper setting of Cable Select 092 Disk Outline MPB3064AT Model HeadMPB 3052AT M odel Air filter SpindleActuator Circuit Configuration MPB30xxAT Block diagram Power-on Sequence Power-on operation sequence Self-calibration contents Command processing during self-calibration Self-calibration execution timechart Write precompensation algorithm Read/write preamplifier PreAMPWrite circuit Read/write circuit block diagram Read circuit Frequency characteristic of programmable filter PR4 signal transfer Time base generator circuit Write clock frequency and transfer rate of each zone Servo control circuit Physical sector servo configuration on disk surface Page PAD Data-surface servo formatServo frame format Actuator motor control Spindle motor control Page Interface Shows the interface signals Host Physical Interface Interface signals Dasp Signal assignment on the connectorSignal assignment on the interface connector Reset Pidag DiorHdmardy Hstrobe Ddmardy Iordy 1 I/O registers DA2 DA1 DA0 I/O registers Icrc UNC Idnf Abrt TK0NF Amnf Command block registersPage DEV HS3 HS2 HS1 HS0 BSY Drdy DSC DRQ ERR Page Srst Control block registers Command code and parameters 1 Command code and parameters Standby Immediate Sleep Check Power Mode Smart Flush Cache Command code and parameters 2 LBA LSB Command descriptionsLBA LBA LSB Read Multiple XC4 BSY Drdy Intrq DRQ Execution example of Read Multiple command LBA LSB LBA LBA Write Multiple XC5 LBA LSB Write Verify X3C LBA LSB 1F4 HCL Cylinder No. LSB / LBA 1F3 HSN Sector No Identify Device XEC Initialize Device ParametersPage Information to be read by Identify Device command 1 Information to be read by Identify Device command 2 Information to be read by Identify Device command 3 Identify Device DMA XEE SET Features XEF ‘CC’ Features register values and settable modes‘AA’ ‘BB’ SET Multiple Mode XC6 Page Diagnostic code Page 1F7 HCM 1F6 HDH Head No. /LBA MSB 1F5 HCH Cylinder No. MSB LBA Write Buffer XE8 Page Page Page Page XFF Page ’DA’ Features Register values subcommands and functionsPage 1FE 1FF Format of device attribute value data Format of insurance failure threshold value data Page Page Page 10 Command code and parameters Error posting Data transferring commands from device to host ∙ Execute Device Diagnostic ∙ Initialize Device Parameters IOR BSYDrdy DRQ Intrq DRQ Intrq BSY Drdy DRQ Intrq Write Sectors command protocol BSY Drdy Intrq Commands without data transfer ∙ Read DMA ∙ Write DMA Other commandsDMA data transfer commands ∙ Read Multiple ∙ Sleep ∙ Write Multiple IOW DRQ Dmarq Dmack Ultra DMA feature set Overview Phases of operation Data in transfer Pausing an Ultra DMA data in burst Terminating an Ultra DMA data in burst Page Page Data out transfer Pausing an Ultra DMA data out burst Terminating an Ultra DMA data out burst Page Ultra DMA CRC rules DIOW-STOP Series termination required for Ultra DMA11 Recommended series termination for Ultra DMA DIOR-HDMARDY-HSTROBE Timing PIO data transfer IOCS16 Iordy DIOR-/DIOW Dmarq Dmack DIOR-/DIOW Single word DMA data transfer Multiword data transfer 11 Multiword DMA data transfer timing mode 12 Initiating an Ultra DMA data in burst Ultra DMA data transfer Dmardy NAM Mode Comment MIN MAX 12 Ultra DMA data burst timing requirements 2 13 Sustained Ultra DMA data in burst Sustained Ultra DMA data in burst 14 Host pausing an Ultra DMA data in burst Host pausing an Ultra DMA data in burst 15 Device terminating an Ultra DMA data in burst Device terminating an Ultra DMA data in burst 16 Host terminating an Ultra DMA data in burst Host terminating an Ultra DMA data in burst 17 Initiating an Ultra DMA data out burst 18 Sustained Ultra DMA data out burst Sustained Ultra DMA data out burst 19 Device pausing an Ultra DMA data out burst Device pausing an Ultra DMA data out burst 20 Host terminating an Ultra DMA data out burst Host terminating an Ultra DMA data out burst 21 Device terminating an Ultra DMA data out burst Pdiag Dasp Power-on and resetBSY Dasp Operations Response to power-on Response to hardware reset Response to software reset Response to diagnostic command MPB Default parameters LS1 LH1 LH2 LS2 Logical addressLS1 LH0 LBA0 LBA1 LBA2 Power save modePage Power commands Alternating defective sectors Spare area Alternate cylinder assignment Data buffer configuration Write DMA, Write Multiple Caching operation∙ Read Sector S ∙ Read Multiple ∙ Read DMA Usage of read segment ∙ Write Sectors ∙ Write DMA ∙ Write Multiple DAP HAP Mis-hit data Empty data Read-ahead data HAP HAP set to hit position for data transfer Partially hit data Lack data Write Cache ∙ Write Sectors ∙ Write Multiple ∙ Write DMA Fujitsu Canada INC Fujitsu Limited