Intel AS/400 RISC Server, 170 Servers manual Hardware Cryptographic API Performance, Bytes/Second

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Table 8.2

Signing Performance

 

Encryption

 

Threads

 

RSA Key Length

i5/OS

 

 

JCE

 

Algorithm

 

 

(Bits)

 

(Transactions/Second)

(Transactions/Second)

 

 

 

 

 

 

 

SHA-1 / RSA

 

1

 

 

1024

 

 

 

 

901

 

197

 

SHA-1 / RSA

 

10

 

 

1024

 

 

 

 

1,155

 

240

 

SHA-1 / RSA

 

1

 

 

2048

 

 

 

 

129

 

30

 

SHA-1 / RSA

 

10

 

 

2048

 

 

 

 

163

 

35

Notes:

 

 

 

 

 

 

 

 

 

 

 

 

y

Transaction Length set at 1024 bytes

 

 

 

 

 

 

y

See section 8.2 for Test Environment Information

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 8.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Digest Performance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Encryption

 

 

 

 

 

i5/OS

 

 

i5/OS

 

JCE

 

JCE

 

 

Threads

 

(Transactions/

 

 

 

(Transactions/

 

Algorithm

 

 

 

(Bytes/ Second)

 

(Bytes/Second)

 

 

 

 

 

 

Second)

 

 

Second)

 

 

 

 

 

 

 

 

 

 

 

 

 

SHA-1

 

1

 

6,753

 

 

110,642,896

 

 

2,295

37,608,172

 

SHA-1

 

10

 

10,875

 

 

178,172,751

 

 

2,954

48,401,773

 

SHA-256

 

1

 

3,885

 

 

63,645,228

 

 

2,049

33,576,523

 

SHA-256

 

10

 

4,461

 

 

73,086,411

 

 

2,392

39,184,923

 

SHA-384

 

1

 

7,050

 

 

115,505,548

 

 

4,020

65,865,327

 

SHA-384

 

10

 

8,075

 

 

132,301,878

 

 

4,634

75,925,668

 

SHA-512

 

1

 

7,031

 

 

115,201,800

 

 

4,217

69,098,731

 

SHA-512

 

10

 

8,060

 

 

132,059,807

 

 

4,801

78,659,561

Notes:

 

 

 

 

 

 

 

 

 

 

 

 

y

Key Length set at 1024 bits

 

 

 

 

 

 

 

 

 

y

Transaction Length set at 16384 bytes

 

 

 

 

 

 

y

See section 8.2 for Test Environment Information

 

 

 

 

 

 

8.4 Hardware Cryptographic API Performance

This section provides information on the hardware based cryptographic offload solution IBM 4764 PCI-X Cryptography Coprocessor (Feature Code 4806). This solution will improve the system CPU capacity by offloading CPU demanding cryptographic functions.

IBM Common Name

IBM 4764 PCI-X Cryptographic Coprocessor

System i hardware feature code

#4806

Applications

Banking/finance (B/F)

 

Secure accelerator (SSL)

Cryptographic Key Protection

Secure hardware module

Required Hardware

No IOP Required

Platform Support

IBM System i5

The 4764 Cryptographic Coprocessor provides both cryptographic coprocessor and secure-key cryptographic accelerator functions in a single PCI-X card. The coprocessor functions are targeted to banking and finance applications. The secure-key accelerator functions are targeted to improving the performance of SSL (secure socket layer) and TLS (transport layer security) based transactions. The 4764 Cryptographic Coprocessor supports secure storage of cryptographic keys in a tamper-resistant module,

IBM i 6.1 Performance Capabilities Reference - January/April/October 2008

 

© Copyright IBM Corp. 2008

Chapter 8 Cryptography Performance

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Intel AS/400 RISC Server, 170 Servers, 7xx Servers manual Hardware Cryptographic API Performance, Bytes/Second