Intel 7xx Servers, 170 Servers manual Model 810 and 825 iSeries for Domino February, V5R2 Additions

C.8.2 Model 810 and 825 iSeries for Domino (February 2003)

Table C.8.2.1. iSeries for Domino			8xx Servers
Model		Chip Speed	L2 cache	CPU	Processor CPW	5250 OLTP	Processor	MCU
		MHz	per CPU	Range		CPW*	CIW*
825-2473 (7416)		1100	1.41 MB	6	6600	0	2890	17400
825-2473	(7416)	1100	1.41 MB	4	na	0	na	11600
810-2469	(7428)	750	4 MB	2	2700	0	950	7900
810-2467	(7410)	750	4 MB	1	1470	0	530	4200
810-2466	(7407)	540	2 MB	1	1020	0	380	3100

*Note: 1. 5250 OLTP CPW - With a rating of 0, adequate interactive processing is available for a single 5250 job to perform system administration functions.

2.IBM does not intend to publish CIW ratings for iSeries after V5R2. It is recommended that the eServer Workload Estimator be used for sizing guidance, available at:

http://www.ibm.com/eserver/iseries/support/estimator

na - indicates the rating is not available for the 4-way processor configuration

C.9 V5R2 Additions

In V5R2 the following new iSeries models were introduced:

y890 Base and Standard models

y840 Base models

y830 Base and Standard models

Base models represent server systems with “0” interactive capability. Standard Models represent systems that have interactive features available and also may have Capacity Upgrade on Demand Capability.

See Chapter 2, iSeries RISC Server Model Performance Behavior, for a description of the performance highlights of the new Dedicated servers for Domino models.

C.9.1 Base Models 8xx Servers

Table C.9.1.1 Base Models 8xx Servers
Model		Chip Speed	L2 cache	CPUs	Processor	Interactive	Processor
		MHz	per CPU		CPW	CPW	CIW	MCU
890-0198 (none)		1300	1.41 MB*	32	37400	0	16700	108900
890-0197	(none)	1300	1.41 MB*	24	29300	0	12900	84100
840-0159	(none)	600	16 MB	24	20200	0	10950	77800
840-0158	(none)	600	16 MB	12	12000	0	5700	40500
830-0153 (none)		540	4 MB	8	7350	0	3220	20910

* 890 Models share L2 cache between 2 processors

C.9.2 Standard Models 8xx Servers

Standard models have an initial offering of processor and interactive capacity with featured upgrades for activation of additional processors and increased interactive capacity. Processor features are offered through Capacity Upgrade on Demand, described in C.10 V5R1 Additions.

IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
© Copyright IBM Corp. 2008	Appendix C CPW, CIW and MCU for System i Platform	353