Table C.4.1. IBM BladeCenter models

Blade Model

Server

Edition

Processor

Chip Speed

L2/L3 cache (1)

CPUs

Processor

Feature

Feature

Feature

MHz

per chip

CPW

 

 

 

 

 

 

 

 

 

 

JS22 (7998-61X)

n/a

n/a

52BE

4000

2x4MB / 0 MB

3 of 4 (2)

11040

 

 

 

 

 

 

 

 

JS22 (7998-61X)

n/a

n/a

52BE

4000

2x4MB / 0 MB

3.7 of 4 (3)

13800

 

 

 

 

 

 

 

 

*Note: 1. These models have a dedicated L2 cache per processor core, and no L3 cache

2.CPW value is for a 3-core dedicated partition and a 1-core VIOS

3.CPW value is for a 3.7-core partition with shared processors and a 0.3-core VIOS partition

C.5 V5R4 Additions (July 2007)

C.5.1 IBM System i using the POWER6 processor technology

Table C.5.1. System i models

 

 

 

 

 

 

 

Model

Server

 

Edition

Processor

Chip Speed

L2/L3 cache (1)

CPU (5)

Processor

(4)

Feature

 

Feature2

Feature

MHz

per chip

Range

CPW

MCU

 

 

 

 

 

 

 

 

 

 

 

 

 

i570 (9406-MMA)

4910

 

5460

7380

4700

2x4MB / 32MB

1 - 4

5500-21200

12300-47500

i570 (9406-MMA)

4911

 

5461

7380

4700

2x4MB / 32MB

2 - 8

10800-40100

24200-89700

i570 (9406-MMA)

4912

 

5462

7380

4700

2x4MB / 32MB

4 - 16

20100-76900

45000-172000

i570 (9406-MMA)

4922

 

7053(3)

7380

4700

2x4MB / 32MB

1 - 4

5500-21200

12300-47500

i570 (9406-MMA)

4923

 

7058(3)

7380

4700

2x4MB / 32MB

1 - 8

5500-40100

12300-89700

i570 (9406-MMA)

4924

 

7063(3)

7380

4700

2x4MB / 32MB

2 - 16

10800-76900

24200-172000

 

 

 

 

 

 

 

 

 

 

*Note: 1. These models have a dedicated L2 cache per processor core, and share the L3 cache between two processor cores.

2.This is the Edition Feature for the model. This is the feature displayed when you display the system value QPRCFEAT.

3.Capacity Backup model.

4.Projected values. See Chapter 11 for more information.

5.The range of the number of processor cores per system.

C.6 V5R4 Additions (January/May/August 2006 and January/April 2007)

C.6.1 IBM System i using the POWER5 processor technology

Table C.6.1.1. System i models

 

 

 

 

 

 

 

Model

Edition

Accelerator

Chip Speed

L2/L3 cache

CPU

 

Processor

5250 OLTP

MCU

Feature2

Feature

MHz

per CPU (1)

Range

CPW

CPW

 

 

 

 

 

 

 

 

 

 

 

 

9406-595

5892

NA

2300

1.9/36MB

32 - 64

(8)

108000-216000

Per Processor

242K(7)- 460K(7)

9406-595

5872

NA

2300

1.9/36MB

32 - 64

(8)

108000-216000

0

242K(7)- 460K(7)

9406-595

5891

NA

2300

1.9/36MB

16 - 32

61000-108000

Per Processor

131K(7)- 242K(7)

9406-595

5871

NA

2300

1.9/36MB

16 - 32

61000-108000

0

131K(7)- 242K(7)

9406-595

5896(4)

NA

2300

1.9/36MB

4 - 32

16000-108000

Per Processor

35800(7)- 242K(7)

9406-595

5876(4)

NA

2300

1.9/36MB

4 - 32

16000-108000

0

35800(7)- 242K(7)

9406-595

5890

NA

2300

1.9/36MB

8-16

31500-58800

Per Processor

68400(7)- 131K(7)

IBM i 6.1 Performance Capabilities Reference - January/April/October 2008

 

 

 

 

© Copyright IBM Corp. 2008

Appendix C CPW, CIW and MCU for System i Platform

 

348

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Image 348
Intel 170 Servers, AS/400 RISC Server manual V5R4 Additions July, V5R4 Additions January/May/August 2006 and January/April