Intel AS/400 RISC Server, 170 Servers, 7xx Servers V6R1 Additions August, V6R1 Additions April

2.Memory speed differences account for some slight variations in performance difference between models.

3.CPW values for Power System models introduced in October 2008 were based on IBM i 6.1 plus enhancements in post-release PTFs.

C.1.4 CPW values for IBM Power Systems - IBM i operating system
	Table C.1.4. CPW values for Power System Models
	Model	Processor	Chip Speed	L2/L3 cache (1)	CPU (2)	Processor
		Feature	GHz	per chip	Range	CPW
	520 (8203-E4A)	5633	4.2	2x4MB / 0MB	1	4300
	520 (8203-E4A)	5634	4.2	2x4MB / 0MB	2	8300
	520 (8203-E4A)	5635	4.2	2x4MB / 0MB	4	15600
	550 (8204-E8A)	4965	3.5	2x4MB / 32MB	2 - 8	7750-27600
	550 (8204-E8A)	4966	4.2	2x4MB / 32MB	2 - 8	9200-32650

*Note: 1. These models have a dedicated L2 cache per processor core, and share the L3 cache between two processor cores.

2.The range of the number of processor cores per system.

3.Memory speed differences account for some slight variations in performance difference between models.

4.CPW values for Power System models introduced in October 2008 were based on IBM i 6.1 plus enhancements in post-release PTFs.

C.2 V6R1 Additions (August 2008)

C.2.1 CPW values for the IBM Power 595 - IBM i operating system

Table C.2.1. CPW values for Power System Models

						Processor CPW
Model	Processor	Chip Speed	L2/L3 cache (1)	8 cores	16 cores		24 cores	32 cores	64 cores (2)
	Feature	MHz	per chip						(2x32)
595 (9119-FHA)	4695	5000	2x4MB / 32MB	41000	77000		108100	147900	294700
595 (9119-FHA)	4694	4200	2x4MB / 32MB	35500	66400		93800	128000	256200

*Note: 1. These models have a dedicated L2 cache per processor core, and share the L3 cache between two processor cores.

2.This configuration was measured with two 32-core partitions running simultaneously on a 64 core system

C.3 V6R1 Additions (April 2008)

C.3.1 CPW values for IBM Power Systems - IBM i operating system

IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
© Copyright IBM Corp. 2008	Appendix C CPW, CIW and MCU for System i Platform	346