Table C.7.1.1. ~® i5 Servers

 

 

 

 

 

 

 

Model

Chip Speed

L2 cache

L3 cache

CPU

Processor

5250 OLTP

MCU

MHz

per CPU (1)

per CPU(2)

Range

CPW

CPW

595-0946 (7497)

1650

1.9 MB

36 MB

8 - 16

24500-45500

12000-45500

54000-104000

595-0946 (7496)

1650

1.9 MB

36 MB

8 - 16

24500-45500

0

54000-104000

570-0926 (7476)

1650

1.9 MB

36 MB

13

- 16

36300-44700

12,000-44,700

83600-102000

570-0926 (7475)

1650

1.9 MB

36 MB

13

- 16

36300-44700

0

83600-102000

570-0926 (7563)5

1650

1.9 MB

36 MB

13

- 16

36300-44700

12000-44,700

83600-102000

570-0928 (7570)4

1650

1.9 MB

36 MB

2 - 16

6350-44700

6,350-44,700

14100-102000

570-0928 (7474)

1650

1.9 MB

36 MB

9 - 12

25500-33400

12,000-33,400

57300-77000

570-0924 (7473)

1650

1.9 MB

36 MB

9 - 12

25500-33400

0

57300-77000

570-0924 (7562)5

1650

1.9 MB

36 MB

9 - 12

25500-33400

12000-44,700

57300-77000

570-0922 (7472)

1650

1.9 MB

36 MB

5

- 8

15200-23500

12,000-23,500

33600-52500

570-0922 (7471)

1650

1.9 MB

36 MB

5

- 8

15200-23500

0

33600-52500

570-0922 (7561)5

1650

1.9 MB

36 MB

5

- 8

15200-23500

12,000-23,500

33600-52500

570-0921 (7495)

1650

1.9 MB

36 MB

2

- 4

6350-12000

12000

14100-26600

570-0921 (7494)

1650

1.9 MB

36 MB

2

- 4

6350-12000

0

14100-26600

570-0921 (7560)5

1650

1.9 MB

36 MB

2

- 4

6350-12000

12000

14100-26600

570-0930 (7491)

1650

1.9 MB

36 MB

1

- 2

3300-6000

6000

7300-13300

570-0930 (7490)

1650

1.9 MB

36 MB

1

- 2

3300-6000

0

7300-13300

570-0930 (7559)5

1650

1.9 MB

36 MB

1

- 2

3300-6000

6,000

7300-13300

570-0920 (7470)

1650

1.9 MB

36 MB

2

- 4

6350-12000

Max

14100-26600

570-0920 (7469)

1650

1.9 MB

36 MB

2

- 4

6350-12000

0

14100-26600

570-0919 (7489)

1650

1.9 MB

36 MB

1

- 2

3300-6000

Max

7300-13300

570-0919 (7488)

1650

1.9 MB

36 MB

1

- 2

3300-6000

0

7300-13300

 

 

 

 

 

 

 

 

 

550-0915 (7530)6

1650

1.9 MB

36 MB

2

- 4

6350-12000

0

14,100-26600

550-0915 (7463)

1650

1.9 MB

36 MB

1

- 4

3300-12000

3,300-12,000

7300-26600

550-0915 (7462)

1650

1.9 MB

36 MB

1

- 4

3300-12000

0

7300-26600

550-0915 (7558)

1650

1.9 MB

36 MB

1

- 4

3300-12000

3,300-12,000

7300-26600

 

 

 

 

 

 

 

 

 

520-0905 (7457)

1650

1.9 MB

36 MB

 

2

6000

3,300-6000

13300

520-0905 (7456)

1650

1.9 MB

36 MB

 

2

6000

0

13300

520-0905 (7555)5

1650

1.9 MB

36 MB

 

2

6000

3,300-6,000

13300

520-0904 (7455)

1650

1.9 MB

36 MB

 

1

3300

3,300

7300

520-0904 (7454)

1650

1.9 MB

36 MB

 

1

3300

0

7300

520-0904 (7554)5

1650

1.9 MB

36 MB

 

1

3300

3,300

7300

520-0903 (7453)

1500

1.9 MB

NA

 

1

2400

2400

5500

520-0912 (7397)

1500

1.9 MB

NA

 

1

2400

60

5500

520-0912 (7395)

1500

1.9 MB

NA

 

1

2400

60

5500

520-0903 (7452)

1500

1.9 MB

NA

 

1

2400

0

5500

520-0903 (7553)5

1500

1.9 MB

NA

 

1

2400

2400

5500

520-0902 (7459)

1500

1.9 MB

NA

1 (3)

1000

1000

2300

)

1500

1.9 MB

NA

1

(3)

1000

0

2300

520-0902 (7458)

 

520-0902 (7552)5

1500

1.9 MB

NA

1 (3)

1000

1000

2300

520-0901 (7451)

1500

1.9MB

NA

1 (3)

1000

60

2300

520-0900 (7450)

1500

1.9 MB

NA

1 (3)

500

30

NA recommended

*Note: 1. 1.9MB - These models share L2 cache between 2 processors.

2.36MB - These models share L3 cache between 2 processors.

3.CPU Range - Partial processor models, offering multiple price/performance points for the entry market.

4.Capacity Backup model.

5.High Availability model.

6.Domino edition.

7.The MCU rating is a projected value.

IBM i 6.1 Performance Capabilities Reference - January/April/October 2008

 

© Copyright IBM Corp. 2008

Appendix C CPW, CIW and MCU for System i Platform

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