Intel 170 Servers, 7xx Servers manual Dedicated Server for Domino, Table C.11.2.1 Model 2xx Servers

Model	Chip Speed	L2 cache	CPUs	Processor CPW	Interactive CPW
	MHz	per CPU
830-2402 (1534)	540	4 MB	4	4200	560
830-2402 (1535)	540	4 MB	4	4200	1050
830-2402 (1536)	540	4 MB	4	4200	2000
830-2403 (1531)	540	4 MB	8	7350	70
830-2403 (1532)	540	4 MB	8	7350	120
830-2403 (1533)	540	4 MB	8	7350	240
830-2403 (1534)	540	4 MB	8	7350	560
830-2403 (1535)	540	4 MB	8	7350	1050
830-2403 (1536)	540	4 MB	8	7350	2000
830-2403 (1537)	540	4 MB	8	7350	4550
840-2418 (1540)	500	8 MB	12	10000	120
840-2418 (1541)	500	8 MB	12	10000	240
840-2418 (1542)	500	8 MB	12	10000	560
840-2418 (1543)	500	8 MB	12	10000	1050
840-2418 (1544)	500	8 MB	12	10000	2000
840-2418 (1545)	500	8 MB	12	10000	4550
840-2418 (1546)	500	8 MB	12	10000	10000
840-2420 (1540)	500	8 MB	24	16500	120
840-2420 (1541)	500	8 MB	24	16500	240
840-2420 (1542)	500	8 MB	24	16500	560
840-2420 (1543)	500	8 MB	24	16500	1050
840-2420 (1544)	500	8 MB	24	16500	2000
840-2420 (1545)	500	8 MB	24	16500	4550
840-2420 (1546)	500	8 MB	24	16500	10000
840-2420 (1547)	500	8 MB	24	16500	16500

C.11.2 Model 2xx Servers

Table C.11.2.1 Model 2xx Servers
Model	Chip Speed	L2 cache	CPUs	Processor CPW	Interactive CPW
	MHz	per CPU
250-2295	200	n/a	1	50	15
250-2296	200	n/a	1	75	20
270-2248 (1517)	400	n/a	1	150	25
270-2250 (1516)	400	n/a	1	370	0
270-2250 (1518)	400	n/a	1	370	30
270-2252 (1516)	450	2 MB	1	950	0
270-2252 (1519)	450	2 MB	1	950	50
270-2253 (1516)	450	4 MB	2	2000	0
270-2253 (1520)	450	4 MB	2	2000	70

C.11.3 Dedicated Server for Domino

	Table C.11.3.1 Dedicated Server for Domino
	Model	Chip Speed		L2 cache	CPUs	Non Domino	Interactive CPW
		MHz		per CPU		CPW
	820-2425	450		2 MB	1	100	0
	820-2426	500		4 MB	2	200	0
	820-2427	500		4 MB	4	300	0
270-2422	400		n/a	1	50	0
	270-2423	450		2 MB	1	100	0
	270-2424	450		4 MB	2	200	0
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
© Copyright IBM Corp. 2008			Appendix C CPW, CIW and MCU for System i Platform				360