Intel 7xx Servers manual V6R1 Additions January, Table C.3.1. CPW values for Power System Models

Models: 7xx Servers 170 Servers AS/400 RISC Server

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Table C.3.1. CPW values for Power System Models

Model

Processor

Chip Speed

L2/L3 cache (1)

CPU (2)

Processor

Feature

MHz

per chip

Range

CPW

 

 

 

 

 

 

 

 

 

 

 

 

 

520 (9407-M15)

5633

4200

2x4MB / 0MB

1

4300

520 (9408-M25)

5634

4200

2x4MB / 0MB

1 - 2

4300-8300

550 (9409-M50)

4966

4200

2x4MB / 32MB

1 - 4

4800-18000

 

 

 

 

 

 

*Note: 1. These models have a dedicated L2 cache per processor core, and share the L3 cache between two processor cores.

2.The range of the number of processor cores per system.

C.3.2 CPW values for IBM BladeCenter JS12 - IBM i operating system

Table C.3.2. IBM BladeCenter models

Blade Model

Processor

Chip Speed

L2/L3 cache (1)

(2)

Processor

Feature

MHz

per chip

CPUs

CPW (3)

 

 

 

 

 

 

JS12 (7998-60X)

52BF

3800

2x4MB / 0 MB

1.8 of 2

7100

 

 

 

 

 

 

*Note: 1. These models have a dedicated L2 cache per processor core, and no L3 cache

2.CPW value is for a 1.8-core partition with shared processors and a 0.2-core VIOS partition

3.The value listed is unconstrained CPW (there is sufficient I/O such that the processor would be the first constrained resource). The I/O constrained CPW value for a 12-disk configuration is approximately 1200 CPW (100 CPW per disk).

C.3.3 CPW values for IBM Power Systems - IBM i operating system

Table C.3.3. CPW values for Power System Models

 

 

 

 

 

Processor CPW

 

 

 

 

 

 

 

 

 

Model

Processor

Chip Speed

L2/L3 cache (1)

2 cores

4 cores

8 cores

16 cores

Feature

MHz

per chip

 

 

 

 

 

 

 

 

 

 

 

 

 

570 (9117-MMA)

5620

3500

2x4MB / 32MB

8150

16100

30100

57600

570 (9117-MMA)

5621/5622

4200

2x4MB / 32MB

9650

19200

35500

68600

570 (9117-MMA)

7380

4700

2x4MB / 32MB

10800

21200

40100

76900

 

 

 

 

 

 

 

 

*Note: 1. These models have a dedicated L2 cache per processor core, and share the L3 cache between two processor cores.

C.4 V6R1 Additions (January 2008)

C.4.1 IBM i5/OS running on IBM BladeCenter JS22 using POWER6 processor technology

IBM i 6.1 Performance Capabilities Reference - January/April/October 2008

 

© Copyright IBM Corp. 2008

Appendix C CPW, CIW and MCU for System i Platform

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Intel 7xx Servers, 170 Servers, AS/400 RISC Server V6R1 Additions January, Table C.3.1. CPW values for Power System Models