Intel 7xx Servers, 170 Servers manual Model 2xx Servers, 10.3 V5R1 Dedicated Server for Domino

Table C.9.1.1 Model 8xx Servers
Model		Chip Speed	L2 cache	CPUs	Processor	Interactive	Processor
		MHz	per CPU		CPW	CPW	CIW	MCU
840-2461	(1545)	600	16 MB	24	20200	4550	10950	77800
840-2461	(1546)	600	16 MB	24	20200	10000	10950	77800
840-2461	(1547)	600	16 MB	24	20200	16500	10950	77800
840-2461	(1548)	600	16 MB	24	20200	20200	10950	77800

Note: 830 models were first available in V4R5.

C.10.2 Model 2xx Servers

Table C.10.2.1 Model 2xx Servers
Model		Chip Speed	L2 cache	CPUs	Processor	Interactive	Processor	MCU
		MHz	per CPU		CPW	CPW	CIW
270-2431 (1518)		540	n/a	1	465	30	185	1490
270-2432	(1516)	540	2 MB	1	1070	0	380	3070
270-2432	(1519)	540	2 MB	1	1070	50	380	3070
270-2434	(1516)	600	4 MB	2	2350	0	840	6660
270-2434	(1520)	600	4 MB	2	2350	70	840	6660

C.10.3 V5R1 Dedicated Server for Domino

Table C.10.3 .1 Dedicated Servers for Domino
Model		Chip Speed	L2 cache	CPUs	NonDomino	Interactive	Processor	MCU
		MHz	per CPU		CPW	CPW	CIW
270-2452	(none)	540	2 MB	1	100	0	380	3070
270-2454	(none)	600	4 MB	2	240	0	840	6660
820-2456 (none)		600	2 MB	1	120	0	385	3110
820-2457 (none)		600	4 MB	2	240	0	840	6660
820-2458 (none)		600	4 MB	4	380	0	1670	11810

IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
© Copyright IBM Corp. 2008	Appendix C CPW, CIW and MCU for System i Platform	356