Intel AS/400 RISC Server manual SB Models, 12 V4R4 Additions, 12.1 AS/400e Model 7xx Servers

C.11.4 SB Models

Table C.11.4.1 SB Models
Model	Chip Speed	L2 cache	CPUs	Processor CPW*	Interactive CPW
	MHz	per CPU
SB2-2315	540	4 MB	8	7350	70
SB3-2316	500	8 MB	12	10000	120
SB3-2318	500	8 MB	24	16500	120

*Note: The "Processor CPW" values listed for the SB models are identical to the 830-2403-1531 (8-way), the 840-2418-1540 (12-way) and the 840-2420-1540 (24-way). However, due to the limited disk and memory of the SB models, it would not be possible to measure these values using the CPW workload. Disk space is not a high priority for middle-tier servers performing CPU-intensive work because they are always connected to another computer acting as the "database" server in a multi-tier implementation.

C.12 V4R4 Additions

The Model 7xx is new in V4R4. Also in V4R4 are the Model 170s features 2289 and 2388 were added. See the chapter, AS/400 RISC Server Model Performance Behavior, for a description of the performance highlights of these new models.

Testing in the Rochester laboratory has shown that for systems executing traditional commercial applications such as RPG or COBOL interactive general business applications may experience about a

5% increase in CPU requirements. This effect was observed using the workload used to compute CPW, as shown in the tables that follows. Except for systems which are nearing the need for an upgrade, we do not expect this increase to significantly affect transaction response times. It is recommended that other sections of the Performance Capabilities Reference Manual (or other sizing and positioning documents) be used to estimate the impact of upgrading to the new release.

C.12.1 AS/400e Model 7xx Servers

MAX Interactive CPW = Interactive CPW (Knee) * 7/6

CPU % used by Interactive @ Knee = Interactive CPW (Knee) / Processor CPW * 100

CPU % used by Processor @ Knee = 100 - CPU % used by Interactive @ Knee

CPU % used by Interactive @ Max = Max Interactive CPW / Processor CPW * 100

	Table C.12.1.1 Model 7xx Servers		(all new Northstar models)
	Model	Chip Speed	L2 cache	CPUs	Processor CPW	Interactive CPW	Interactive CPW
		MHz	per CPU			(Knee)	(Max)
	720-2061 (Base)	200	n/a	1	240	35	40.8
	720-2061 (1501)	200	n/a	1	240	70	81.7
	720-2061 (1502)	200	n/a	1	240	120	140
	720-2062 (Base)	200	4 MB	1	420	35	40.8
	720-2062 (1501)	200	4 MB	1	420	70	81.7
	720-2062 (1502)	200	4 MB	1	420	120	140
	720-2062 (1503)	200	4 MB	1	420	240	280
	720-2063 (Base)	200	4 MB	2	810	35	40.8
	720-2063 (1502)	200	4 MB	2	810	120	140
	720-2063 (1503)	200	4 MB	2	810	240	280
	720-2063 (1504)	200	4 MB	2	810	560	653.3
	720-2064 (Base)	255	4 MB	4	1600	35	40.8
	720-2064 (1502)	255	4 MB	4	1600	120	140
	720-2064 (1503)	255	4 MB	4	1600	240	280
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
© Copyright IBM Corp. 2008		Appendix C CPW, CIW and MCU for System i Platform					361