Intel 273246-002 manual

Celeron™ Processor

Development Kit Manual

July 1999

Order Number: 273246-002

Contents

Main Page Contents 1 About This Manual 2 Getting Started 3 Theory of Operation 4 Hardware Reference 5 BIOS Quick Reference A PLD Code Listing B Bill of Materials C Schematics Index Figures Tables Page About This Manual 1.1 Content Overview 1.2 Text Conventions 1.3 Technical Support 1.3.1 Electronic Support Systems 1.3.1.1 Online Documents 1.3.1.2 Intel Product Forums 1.3.2 Telephone Technical Support 1.4 Product Literature 1-4 1.5 Related Documents Table 1-1. Related Documents Getting Started 2.1 Overview 2.1.1 Processor Assembly Features 2.1.2 Baseboard Features 2.2 Included Hardware 2.3 Software Key Features 2.3.1 General Software, Inc. 2.3.2 QNX Software Systems, Ltd. 2.4 Before You Begin 2.5 Setting up the Evaluation Board 2.6 Configuring the BIOS Page Theory of Operation 3-1 3.1 Block Diagram Figure 3-1. Evaluation Board Block Diagram 3.2 System Operation 3.2.1 Celeron Processor 3.2.2 82443BX Host Bridge/Controller 3.2.2.1 System Bus Interface 3.2.3 ITP 3.2.4 82371EB PCI to ISA/IDE Xcelerator (PIIX4E) 3.2.5 DRAM 3.2.6 Power 3.2.7 Boot ROM Page 3.2.19 Post Code Debugger 3.2.20 Clock Generation 3.2.21 Interrupt Map 3-7 3.2.22 Memory Map Table 3-2. Memory Map Page Hardware Reference 4.1 Processor Assembly 4.1.1 Thermal Management 4.1.2 ITP Debugger Port 4.2 Post Code Debugger Page 4-3 4.5 Connector Pinouts 4.5.1 ATX Power Connector 4-4 4.5.2 ITP Debugger Connector 4.5.3 Stacked USB P0 is the bottom connector. P1 is on top. Table 4-3. ITP Connector Pin Assignment (J2 on the Processor Assembly) Table 4-4. USB Connector Pinout (J2) 4.5.4 Mouse and Keyboard Connectors The keyboard port is on top. The mouse port is on the bottom. 4.5.5 Parallel Port Table 4-5. Keyboard and Mouse Connector Pinouts (J1 on the Baseboard) Table 4-6. DB25 Parallel Port Connector Pinout (J3) 4.5.6 Serial Ports COM1 is the top connector. COM2 is the bottom connector. 4.5.7 IDE Connector Table 4-7. Serial Port Connector Pinout (J4) Table 4-8. PCI IDE1 (JP3) and IDE2 (JP4) Connector 4.5.8 Floppy Drive Connector Table 4-9. Diskette Drive Header Connector (JP1) 4-8 4.5.9 PCI Slot Connector Table 4-10. PCI Slots (J7, J8, J9) 4-9 4.5.10 ISA Slot Connector Table 4-11. ISA Slots (J5, J6) 4-10 4.6 AGP Connector Table 4-12. AGP Slot (J13) 4.7 Jumpers 4.7.1 Enable Spread Spectrum Clocking (J14) 4.7.2 Clock Frequency Selection (J15) 4.7.3 On/Off (J20) 4.7.4 Flash BIOS VPP Select (J21) 4.7.5 Flash BIOS Boot Block Control (J22) 4.7.6 SMI# Source Control (J23) 4.7.7 CMOS RAM Clear (J24) 4.7.8 Push Button Switches 4.8 In-Circuit BIOS Update Page BIOS Quick Reference 5.1 BIOS and Pre-Boot Features 5.2 Power-On Self-Test (POST) Page 5.3 Setup Screen System 5.3.1 Basic CMOS Configuration Screen 5.3.2 Configuring Drive Assignments 5.3.2.1 Configuring Floppy Drive Types 5.3.3 Configuring IDE Drive Types 5.4 Configuring Boot Actions 5.5 Custom Configuration Setup Screen 5.6 Shadow Configuration Setup Screen 5.7 Standard Diagnostics Routines Setup Screen 5.8 Start System BIOS Debugger Setup Screen 5.9 Start RS232 Manufacturing Link Setup Screen 5.10 Manufacturing Mode 5.10.1 Console Redirection 5.10.2 CE-Ready Windows CE Loader 5.10.3 Integrated BIOS Debugger Page 5-12 5.11 Embedded BIOS POST Codes 5-13 5-14 5.12 Embedded BIOS Beep Codes Page A-1 PLD Code Listing A The code listing below is for the 22V10 PLD. A-2 PLD Code Listing B-1 Bill of Materials B B-2 Table B-1. Baseboard Bill of Materials (Sheet 2 of 4) B-3 Table B-1. Baseboard Bill of Materials (Sheet 3 of 4) B-4 Table B-1. Baseboard Bill of Materials (Sheet 4 of 4) B-5 Table B-2. Celeron Processor Assembly Bill of Materials (Sheet 1 of 2) B-6 Table B-2. Celeron Processor Assembly Bill of Materials (Sheet 2 of 2) Schematics C Evaluation Platform Revision D History System Electronics Board Page Mini PCI Connector Note:GFBCLK must be 3.0" longer than GCKOUT CPU Connector Slave address 10100000b Socket 0 DIMM0 Slave address 10100001b Socket 1 DIMM1 Slave address 10100010b Socket 2 Note: J16 is not populated DIMM2 Stuff only to enable These caps can be tuned to Note: R11 and R12 should be placed as lengths should be equal. caps close to crystal. All lead Keep crystal close to clock and TX/Pentium Designs. Note only ISA Pullups PCI Pullups is on PIIX4 page Note IRQ8 Pull-up ISA/PCI Pullups PCI SLOT 0 PCI SLOT 1 -12V: B1 J7/J8 +12V: A2 B57 B3, B12, B13, B15, B17, B28, B34, B38, B46, B49, PCI SLOT 2 PCI Slot 2 Stub length from connector to resistor Pin A3 is tied to ground per AGP Specification must be less than 0.1" Rev 1.0 AGP Connector PIIX4 CPU Module must drive 1-2 Normal Operation should be equal Trace lengths DMA/IRQ USB INTERFACE POWER MGMT. CPU Primary IDE Connector Secondary IDE Connector HD Active LED IDE Connectors PULL romCs# high so as not to Floppy configure IRQs BIOS needs to enable and This disables the ROM buffers. Do not stuff NOTE 1: USB differential traces route together (Z0- & Z0+) and (Z1- & Z1+). TOP of Stacked of USB Connector stack Place these caps within 1 inch Poly fuses should be in range ISA Slots J5/J6 V5_0: Note Cap Direction Note Cap Direction -12V B07 J5/J6: +12V B09 COM0/COM1 FLOPPY FLOPPY HEADER 17X2 PARALLEL COM0 Port 80 Expect All 0's except Option Stuff SA7=1 for P80 Decode Standard SPEAKER HEADER PS_OK = OR of PW_OK,-DBRESET,RESET SWITCH Note: Add screen marking for V5_0 LED, V3_3 LED AXT Power Connector Unused Gates Revision Celeron(TM) Processor A1 in PPGA Daughter Board Page THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO 370 Pin Socket OTHERWISE ARISING OUT OF PROPOSAL, ANY PARTICULAR PURPOSE, OR ANY WARRANTY WARRANTY OF MERCHANTABILITY, FITNESS FOR WARRANTIES WHATSOEVER, INCLUDING ANY 370 Pin Socket Power Supply Resistor Packs placed for Dual End Termination. Single End Termination. Not used on Celeron Processor in PPGA package with GTL+ TERMINATION RESISTORS-BX GTL+ TERMINATION VOLTAGE RESISTORS-CPU Note: PCI 5V PCI INTERFACE AGP INTERFACE PCI ARB & PWR MGT HOST INTERFACE BX Strapping Options MEMORY INTERFACE AGP clock signals Mounting Holes GCLKO_B+G_CLKOUT should all be the same Layout: G_CLKIN,GCLKO_A+G_CLKOUT, length UNUSED GATES BUS RATIO SELECT 110 Current Address: 1001 Address Select Straps FOR PROCESSOR Note: AGND must tie GROUND PLANE. TIE DIRECTLY TO output CAP. DO NOT directly to nearest Index A B C D K M N O P