| 5 | 4 | 3 | 2 | 1 |
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D
C
B
A
Evaluation Platform
System Electronic s Board
Revision D
THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER,NCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION ORSAMPLE.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification.Intel does not warrant or represent that such use will not infringe such rights.
History
Changes made to Revisio n D.
1.Added Signals PWROK(A24) +12V(A33) MB12#_R(B33 ) to J19A.
2.Moved J2 0
3.Added C229 to
Changes made to Revisio n C.
1.Tied VBAT (pin 65) to 3.3V on Supe r I/O.
Changes made to Revisio n B.
1.Swapped AD23 and AD19 on 400 pin con nector.
2.Separated CSEL on IDE0 and IDE1
3.Swapped pins 1 and 3 (V5 with TP) on
4.Tied VBAT (pin 65) to 5.0V on Sup er I/O.
5.Changed RP48 to 4.7K. (Pullups for mouse and k eyboard.)
6.Inverted POWERON# signal (SUSC#) from PIIX4 to control soft- on feature.
7.Changed Bulk decoupling on +12 and
8.Changed Bulk decoupling cap C154 from 10uF to 47uF to reduce BO M line items.
THIS DRAWING CONTAINS INFORMATION WHICH HASNOT
BEEN VERIFIED FOR MANUFACTURING AS AN END SERU
PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE
MISUSE OF THIS INFORMATION.
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Title | Changes |
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Size | Document Number |
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| Rev |
C |
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| D |
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Date: | Thursday, February 25, 1999 | Sheet | 1 of 2 2 |
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D
C
B
A
| 5 | 4 | 3 | 2 | 1 |
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