Intel 273246-002 manual Been Verified for Manufacturing AS AN Enduser Title

A B C D E

4

3,4,10,11	AD[31:0]
				AD0
				AD1
				AD2
				AD3
				AD4
				AD5
				AD6
				AD7
				AD8
				AD9
				AD10
				AD11
				AD12
				AD13
				AD14
				AD15
				AD16
				AD17
			AD18	AD18
				AD19
				AD20
				AD21
				AD22
				AD23
				AD24
				AD25
				AD26
				AD27
				AD28
	R39			AD29
	2 2 0			AD30
				AD31
	3,4,10,11 -C/BE[3:0]			-C/BE0
				-C/BE1
				-C/BE2
				-C/BE3
PIIX4 is PCI
device #8		3,4	CLKRUN#
	R _ AD18	3,4,9,10,11	- DEVSEL
		3,4,9,10,11	- FRAME

B 1 0 A 1 0 D9 C9 B 9 A 9 D8 E 8 B 8 A 8 D7 C7 B 7 A 7 D6 E 6 E 4 C4 B 4 A 4 D3 E 3 C3 B 3 E 2 C2 B 2 A 2 D1 E 1 C1 B 1

C8

C6

D4

D2

C10

E 5

A 5

A 3

U8A

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

C/BE#0

C/BE#1

C/BE#2

C/BE#3

CLOCKRUN#

DEVSEL#

FRAME# IDSEL

IDE

SIGNALS

PCI

SIGNALS

PIIX4

SDD0

SDD1

SDD2

SDD3

SDD4

SDD5

SDD6

SDD7

SDD8

SDD9

SDD10

SDD11

SDD12

SDD13

SDD14

SDD15

DS3S#

DS3P#

DS1S#

DS1P#

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

S A 1 0

S A 1 1

S A 1 2

S A 1 3

S A 1 4

S A 1 5

S A 1 6

S A 1 7

S A 1 8

S A 1 9

		SDD[15:0]	1 5
E 1 5	SDD0
B 1 5	SDD1
D14	SDD2
C14	SDD3
A 1 4	SDD4
C13	SDD5
A 1 3	SDD6
C12	SDD7						4
D12	SDD8
B 1 3	SDD9
D13	SDD10				U21B
B 1 4	SDD11		RSTDRV	3	4
E 1 4	SDD12					RSTDRV#	1 5
A 1 5	SDD13
C15	SDD14
D15	SDD15				74HCT14
C18	SDCS3#	1 5
H16
	PDCS3#	1 5
B 1 8
	SDCS1#	1 5
H17
	PDCS1#	1 5
U11	SA0	SA[19:0]	9,16,18,20
T 1 1	SA1
W 1 1	SA2
Y11	SA3
T 1 0	SA4
W 1 0	SA5
U9	SA6
V 9	SA7
Y9	SA8
T 8	SA9
W 8	S A 1 0
U7	S A 1 1
V 7	S A 1 2
Y7	S A 1 3
V 6	S A 1 4
Y6	S A 1 5
T 5	S A 1 6
W 5	S A 1 7
U4	S A 1 8
V 4	S A 1 9				XD[7:0]	2 0

3

2

1

3,4,10,11,12 -PCIRST

Place near PIIX4 C 2 2 9

4 7 p F

1 5 PDD[15:0]

3,4,9,10,11		-IRDY
3,4,9,10,11 PAR
4,9	- PHOLD
4,9	- PHOLDA
3,4,9,10,11		- SERR
3,4,9,10,11		- S T O P
3,4,9,10,11		- TRDY
4,9,10		- PREQ0
4,9,10		- PREQ1
4,9,11		- PREQ2
3,4,9		- PREQ3

PDD0

PDD1

PDD2

PDD3

PDD4

PDD5

PDD6

PDD7

PDD8

PDD9

PDD10

PDD11

PDD12

PDD13

PDD14

PDD15

1 5 SDA0

1 5 SDA1

1 5 SDA2

1 5 PDDACK#

1 5 SDDACK#

1 5 PDREQ

1 5 SDREQ

1 5 PDIOR#

1 5 PDIOW#

1 5 PIORDY

1 5 SDIOR#

1 5 SDIOW#

1 5 SIORDY

1 5 PDA0

1 5 PDA1

1 5 PDA2

B 5

B 6

A 1

B 1 2 A 1 2 A 6 D5 C5

E 1 0 A 1 1 B 1 1 C11

F 2 0 E 1 8 E 2 0 D18 D20 C20 B 2 0 A 2 0 A 1 9 B 1 9 C19 D19 D17 E 1 9 E 1 7 F 1 9

C17 B 1 7 A 1 8 G 1 9 A 1 7 F 1 8 A 1 6 F 1 7 F 1 6 G 2 0 C16 B 1 6 D16 G 1 6 G 1 8 G 1 7

IRDY#

PAR PCIRST# PHOLD# PHOLDA# SERR#

S T O P #

TRDY#

R E Q 0 #

R E Q 1 #

R E Q 2 #

R E Q 3 #

PDD0

PDD1

PDD2

PDD3

PDD4

PDD5

PDD6

PDD7

PDD8

PDD9

PDD10

PDD11

PDD12

PDD13

PDD14

PDD15

SDA0

SDA1

SDA2

PDDACK#

SDDACK#

PDREQ#

SDREQ#

PDIOR#

PDIOW# PIORDY SDIOR# SDIOW# SIORDY PDA0 PDA1 PDA2

PIIX4E

ISA/EIO

SIGNALS

IDE

SIGNALS

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD8

SD9

SD10

SD11

SD12

SD13

SD14

SD15

G P O 1 / L A 1 7 G P O 2 / L A 1 8 G P O 3 / L A 1 9 G P O 4 / L A 2 0 G P O 5 / L A 2 1 G P O 6 / L A 2 2 G P O 7 / L A 2 3

M E M C S 1 6 # M E M R # M E M W #

S M E M R #

S M E M W #

SYSCLK GPO0/BALE GPI0/IOCHK#

REFRESH#

IOCS16#

ZEROWS#

SBHE#

RSTDRV

IOR#

IOW#

IOCHRDY

AEN

SD[15:0]

9,16,18,20

U7

3

V 3

SD0

SD0

2

1 8

XD0

A 1

B 1

W 3

SD1

SD1

3

1 7

XD1

A 2

B 2

U2

SD2

SD2

4

1 6

XD2

A 3

B 3

T 2

SD3

SD3

5

1 5

XD3

A 4

B 4

W 2

SD4

SD4

6

1 4

XD4

A 5

B 5

Note: U14, C203,C215, C210 , R50

Y2

SD5

SD5

7

1 3

XD5

A 6

B 6

T 1

SD6

SD6

8

1 2

XD6

V 1

SD7

SD7

9

A 7

B 7

1 1

XD7

and R51 are not popula ted

A 8

B 8

W 1 6

SD8

T 1 6

SD9

1 4

X O E #

1 9

G

Y17

SD10

1

V 1 7

SD11

1 4

XDIR#

DIR

V 5 _ 0

Y18

SD12

7 4 A L S 2 4 5

W 1 8

SD13

Y19

SD14

W 1 9

SD15

C 2 0 3

C 2 1 5

C 2 1 0

L A 1 7

LA[23:17]

9,18

0 . 1uF

0 . 1uF

0 . 1uF

Y15

T 1 4

L A 1 8

W 1 4

L A 1 9

U14

64 19 51

U13

L A 2 0

V 1 3

L A 2 1

VCC VCC

VCC

Y13

L A 2 2

5 9

4

T 1 2

L A 2 3

D0

APICD0

APICD0

4,9

5 8

5

D1

APICD1

APICD1

4,9

5 7

6 2

D2

APICCLK

APICCLK0

8

Y12

M E M C S 1 6 #

9,18

5 6

D3

V 1 5

5 5

M E M R #

9,18,20

D4

U15

5 4

1 7

M E M W #

9,18,20

D5

INTIN0

INTR

4,9,14

W 4

5 3

3 4

S M E M R #

9,18

D6

INTIN1

IRQ1

9,14,16

5 0

3 5

D7

INTIN2

IRQ0

1 4

U3

2 5

S M E M W #

9,18

SA4

INTIN3

IRQ3

9,14,16,18

T 7

1 5

2 6

SYSCLK

1 8

D/I#

INTIN4

IRQ4

9,14,16,18

U10

SA0

1 3

2 7

BALE

9,18

A 0

INTIN5

IRQ5

9,14,16,18

Y1

SA1

1 4

2 8

IOCHK#

9,18

A 1

INTIN6

IRQ6

9,14,16,18

M E M R #

1 2

2 9

RD#

INTIN7

IRQ7

9,14,16,18

W 7

REFRESH#

9,18

M E M W #

1 1

3 1

IRQ8_Buf

WR#

INTIN8

2

V 1 2

IOCS16#

9,18

9,14

APICCS#

6 1

CS#

INTIN9

3 0

IRQ9

9,14,18

Y3

ZEROWS#

9,18

INTIN10

2 4

IRQ10

9,14,16,18

9

2 3

1 4

APICREQ#

APICREQ#

INTIN11

IRQ11

9,14,18

W 1 2

1 0

2 2

SBHE#

9,18

1 4

APICACK1#

APICACK1#

INTIN12

I13R

IRQ12

9,14,16,18

W 1

8

1 6

RSTDRV

16,18

4

WSC#

APICACK2#

INTIN13

Y5

1 8

IOR#

9,16,18

INTIN14

IRQ14

9,14,15,16,18

T 4

2

2 1

IOW#

9,16,18,20

8

PCLKAPIC

RSTDRV

PCICLK

INTIN15

IRQ15

9,14,15,16,18

T 3

6 0

3 7

IOCHRDY

9,16,18

R E S E T

INTIN16

PIRQA#

3,9,10,11,14

Y4

3 8

AEN

16,18,20

V 5 _ 0

INTIN17

PIRQB#

3,9,10,11,12,14

3 9

INTIN18

PIRQC#

3,9,10,11,12,14

3

4 0

TESTIN#

INTIN19

PIRQD#

3,9,10,11,14

4 1

RP59

INTIN20

I21R

IRQ9OUT#

1 4

4 2

8

1

7

INTIN21

4 3

I22R

I13R

NC

INTIN22

7

2

2 0

4 4

PX4 _ SMI#

1 4

NC

INTIN23/SMI#

6

3

I21R

3 2

6

NC

SMIOUT#

5

4

I22R

3 6

NC

4 5

NC

1 0 K

4 6

NC

4 7

NC

4 8

1

J23

NC

4 9

NC

6 3

2

SMI#

4

NC

RSTDRV

JUMP3

3

V3.3SUS

V2.5

1

GND

GND GND

2

D4

Bat54

8 2 0 9 3 A A

1 33 52

R50

1 K

This circuit is to prevent IOAPIC

R 1 1 7

1 0 K

3

from being powered by IRQ#8

R51

1 K

when in suspend and power

1

is not applied to device.

1

1 4

1 4

IRQ#8

2

3

IRQ8_Buf

7

U15A

7 4 L V C 1 2 5

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT

BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title

PIIX4 Part 1

PRODUCT.

INTEL IS NOT RESPONSIBLE FORTHE

Size

Document Number

Rev

MISUSE OF THIS INFORMATIO.

C

{Doc}

D

Date:

Thursday, February 25, 1999

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1 3 of

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