Intel 273246-002 manual ISA/Host

A

9,13,18,20 SD[15:0]

4

9,13,18,20 SA[19:0]

			13,18,20	AEN
			9,13,18	IOCHRDY
			13,18	RSTDRV
		9,13,14,15,18		IRQ15
		9,13,14,15,18		IRQ14
			9,14,18	DRQ0
			9,14,18	DRQ1
			9,14,18	DRQ2
			9,14,18	DRQ3
			14,18	DACK0#
			14,18	DACK1#
			14,18	DACK2#
3			14,18	DACK3#
			14,18	T C
			9,13,18	IOR#
		9,13,18,20		IOW#
				8	REF1
		1 4	K B D R S T #
		1 4	K B D A 2 0 G A T E
		9,13,14	IRQ1
		9,13,14,18	IRQ3
	V 5 _ 0	9,13,14,18	IRQ4
		9,13,14,18	IRQ5
		9,13,14,18	IRQ6
		9,13,14,18	IRQ7
		R11	IRQ10
		9,13,14,18
		9,13,14,18	IRQ12
		1 0 K

					B						C			D	E
					V 5 _ 0 V 3 _ 3 V 5 _ 0
	C 1 6 0		C 1 6 1	C 1 5 9
	0 . 1uF		0 . 1uF	0 . 1uF
		U1		62	93 121 69	65	19	20 21
SD0	4 4			VCC VCC VCC		VTR VBAT	POWERON BUTTON IN PME#/IRQ9						Install for 370 Config
		SD0											address
SD1	4 5									1 6	- RDATA	1 9
		SD1							R D A T A #						4
SD2	4 6									1 1
		SD2							W G A T E #		- W G A T E	1 9
SD3	4 7	SD3							W D A T A #	1 0	- W D A T A	1 9
SD4	4 9									1 2
		SD4							HDSEL#		-SIDE1	1 9
SD5	5 0									8				V 5 _ 0
		SD5							DIR#		-DIR	1 9
SD6	5 1									9
		SD6				Floppy			S T E P #		- S T E P	1 9	R5
SD7	5 2									1 7
		SD7							DSKCHG#		- DSKCHG	1 9
										5
SA0	2 3								DS0#	6	- DRVSA	1 9
		SA0							DS1#		- DRVSB	1 9
SA1	2 4									3
		SA1							M T R 0 #		- M O T E A	1 9	1 0 K
SA2	2 5									4
		SA2							M T R 1		- M O T E B	1 9
SA3	2 6									1 5
		SA3							W R T P R T #		- W P T	1 9		Install only one
SA4	2 7									1 4
		SA4							T R K 0 #		- T R K 0	1 9
SA5	2 8	SA5							INDEX#	1 3	-INDEX	1 9		resistor!
SA6	2 9	SA6							DRVDEN0	1	HDEN	1 9	R6
SA7	3 0									2
		SA7		ISA/Host					DRVDEN1		D R A T E 0	1 9
SA8	3 1
		SA8								1 1 2
SA9	3 2								RXD1		RXD0	1 9
S A 1 0	3 3	SA9								1 1 3
		S A 1 0							T X D 1		T X D 0	1 9	1 K
S A 1 1	3 4									1 1 5
		S A 1 1							RTS1#/SYSOP		R T S 0 #	1 9
S A 1 2	3 5									1 1 6
		S A 1 2							C T S 1 #		C T S 0 #	1 9	Do not stuff
S A 1 3	3 6									1 1 7
		S A 1 3				Uarts			D T R 1 #		D T R 0 #	1 9
S A 1 4	3 7	S A 1 4							DSR1#	1 1 4	DSR0#	1 9
S A 1 5	3 8									1 1 9
		S A 1 5							DCD1#	1 1 8	DCD0#	1 9
									RI1#		RI0#	1 9	Install for 3F0 Config
	4 3									1 2 3
		AEN							RXD2/IRRX		RXD1	1 9
	6 4	IOCHRDY							TXD2/IRTX	1 2 4	T X D 1	1 9	address
	5 3									1 2 6
		RESET _ DRV							R T S 2 #		R T S 1 #	1 9
	4 0									1 2 7
		SER/IRQ15							C T S 2 #		C T S 1 #	1 9
	3 9									1 2 8
		PCI_CLK/IRQ14/GP50							D T R 2 #		D T R 1 #	1 9
	5 5									1 2 5
		DRQ0							DSR2#		DSR1#	1 9
	5 7									1 2 2
		DRQ1							DCD2#		DCD1#	1 9
	5 9									1 2 0
		DRQ2							RI2#		RI1#	1 9
	6 1
		DRQ3
	5 4
		DACK0#
	5 6
		DACK1#
	5 8									9 6	PDR0	1 9
		DACK2#							PD0
	6 0									9 7
		DACK3#							PD1		PDR1	1 9
	6 3									9 8					3
	4 1	T C							PD2	9 9	PDR2	1 9
		IOR#							PD3		PDR3	1 9
	4 2									1 0 0
		IOW#							PD4		PDR4	1 9
										1 0 1
									PD5		PDR5	1 9
										1 0 2
					Parallel				PD6		PDR6	1 9
	2 2									1 0 3
		C L O C K 1 4							PD7		PDR7	1 9
	6 6									9 5
	6 8	X T L 1							SLCTIN#	9 4	-SLCTRIN	1 9
		X T L 2							PINIT#		-INIT	1 9
	1 8	C L K 3 2 O U T							A L F #	1 1 0	- ALF	1 9
										1 1 1
									S T R O B E #		- S T R O B E	1 9
										1 0 7
									BUSY		-BUSY	1 9
										1 0 8
									ACK#		- ACK	1 9
	7 0									1 0 6
		K D A T							PE		PE	1 9
	7 1									1 0 5
		KCLK							S L C T		S L C T	1 9
	7 2									1 0 9
		M D A T							ERROR#		- ERR	1 9
	7 3
		M C L K
	7 5
		K B D R S T #
	7 6
		A 2 0 M								7 7
									G P 1 0
	8 3									7 8
		IRQ1							G P 1 1
	8 4									7 9
		IRQ3							G P 1 2
	8 5									8 0
		IRQ4							G P 1 3
	8 6									8 1
		IRQ5							G P 1 4
	8 7									8 2
		IRQ6							G P 1 5
	8 8
		IRQ7
	8 9
		IRQ8
	9 0
		IRQ10
	9 1
		IRQ11/ROMCS#
	9 2
		IRQ12
					AVSS	VSS VSS	VSS VSS

2

1

This disables the ROM buffers. BIOS needs to enable and configure IRQs

PULL romCs# high so as not to interfere with boot rom!

A

FDC37B78X 67 7 48 74 104

2

V 5 _ 0

V 5 _ 0

-002

SMD250

F 3

8 7 6 5

2

RP48

2

FB9

4 .7K

B L M 4 1 A 8 0 0 S

1

1 2 3 4

1

FB8

J1

1

2

T 1

1

2

K B D A T A

T 2

NC

B L M 4 1 A 8 0 0 S

T 3

GND

FB5

T 4

KB _ VCC

1

2

T 5

1

2

KB _ CLK

TOP

T 6

B L M 4 1 A 8 0 0 S

NC

1 3

GND

1 4

GND

1 5

GND

1 6

GND

1 7

FB7

GND

1

2

B 1

1

2

M D A T A

B 2

1

B L M 4 1 A 8 0 0 S

B 3

NC

GND

FB6

B 4

M _ VCC

BOTTOM

1

2

B 5

1

2

M _ C L K

B 6

B L M 4 1 A 8 0 0 S

NC

P S 2 S T A C K

C29

C30

C28

C31

C32

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT

4 7 0 p F

4 7 0 p F

4 7 0 p F

4 7 0 p F

4 7 0 p F

BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER

Title

SuperO I/

PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE

Size

Document Number

Rev

MISUSE OF THIS INFORMATIO.

C {Doc}

D

Date:

Thursday, February 25, 1999

Sheet 1 6 of 2 2

B

C

D

E