Hardware Reference
4.5.2ITP Debugger Connector
Table 4-3. ITP Connector Pin Assignment (J2 on the Processor Assembly)
Pin | Signal | Pin | Signal |
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1 | RESET# | 16 | PREQ0# |
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2 | GND | 17 | GND |
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3 | DBRESET# | 18 | PRDY0# |
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4 | GND | 19 | GND |
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5 | TCK | 20 | PREQ1# |
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6 | GND | 21 | GND |
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7 | TMS | 22 | PRDY1# |
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8 | TDI | 23 | GND |
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9 | POWERON | 24 | PREQ2# |
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10 | TDO | 25 | GND |
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11 | DBINST# | 26 | PRDY2# |
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12 | TRST# | 27 | GND |
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13 | GND | 28 | PREQ3# |
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14 | BSEN# | 29 | BCLK |
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15 | GND | 30 | PRDY3# |
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4.5.3Stacked USB
P0 is the bottom connector. P1 is on top.
Table 4-4. USB Connector Pinout (J2)
Pin | P0 Signals | P1 Signals |
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1 | VCC0 | VCC1 |
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2 | D0- | D1- |
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3 | D0+ | D1+ |
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4 | GND0 | GND1 |
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Celeron™ Processor Development Kit Manual |
