Figure 17. Clock Block Diagram
| CPU0_BCLK |
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| CPU0 |
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| CPU1_BCLK |
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| CPU1 |
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| ITP_BCLK |
| DDRA_CMDCLK[0..3] | DDRA |
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| ITP |
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| MCH_BCLK |
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| MCH_66MHZ_CLK |
| DDRB_CMDCLK[0.3] | DDRB |
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| MCH |
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| ICH_USB_48MHZ_CLK |
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| MCH SRC |
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SMA | LPC_14MHZ_CLK |
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ICH_33MHZ_CLK |
| ICH_PX_PCLK0[0..1] |
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| ICH |
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| ICH_HI66MHZ_CLK |
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| 100MHZ CLK |
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| ICH_PX66MHZ_CLK |
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| ICH SRC 100MHZ |
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14.318 MHz | SIO_33MHZ_CLK | 32.786 kHz | ICH SUSCLK |
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LPC_14MHZ_CLK | SIO |
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| PCI Express | ||||
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| MIDBUS_100MHZ_CLK | ||
| LAI_HI66MHZ_CLK |
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| CLK |
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| Midbus Probe |
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| HI LAI |
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| DB800_SRC_100MHZ_CLK |
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| 29.499 MHz |
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| EXP_SLOT3_100MHZ_CLK | PCI Express | ||
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| Slot |
| VIDEO_33MHZ_CLK |
| Video |
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| EXP_SLOT4_100MHZ_CLK |
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| PCI Express | |||
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| FWH_33MHZ_CLK |
| FWH |
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| Slot |
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| PORT80_33MHZ_CLK |
| Port 80 |
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| EXP_SLOT5_100MHZ_CLK | PCI Express | |
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| DB800 |
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| Slot | |
| PCI_SLOT6_33MHZ_CLK |
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| PCI 2.2 |
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| TPM_33MHZ_CLK |
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| TPM |
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3.3.11Platform Resets
Figure 18 depicts the reset logic for the CRB. The 6300ESB provides most of the reset, following assertion of power good and system reset.
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User’s Manual | April 2007 |
32 | Order Number: |
