Figure 18. | Platform Reset Diagram |
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| FWH | TPM | PCI 32 |
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| PCIRST2# |
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| VGA | Port 80 |
| IDERST# | PCIRST1# |
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| IDE | SIO |
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| LPC |
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| CPU 0 |
| Debug | N |
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| SYS_RESET# | PCIRST_ |
| MCH | CPURST# |
| ICH |
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| CPU 1 | |
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| VRM_PWRGD |
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| ITP |
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| SYS_PWRGD_3V3 |
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| Slots |
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3.3.12 | SMBus |
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Figure 19 below illustrates the routing of the SMBus signal among the components.
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April 2007 | User’s Manual |
Order Number: | 33 |
