Intel E7520 user manual Platform Management, Power Button, Sleep States Supported

Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH

4.0Platform Management

The following sections describe how the system power management operates, and how the different ACPI states are implemented. Platform management involves:

•ACPI implementation-specific details

•System monitoring, control, and response to thermal, voltage, and intrusion events

•BIOS security

4.1Power Button

The system power button is connected to the I/O controller component. When the button is pressed, the I/O controller receives the signal and transitions the system to the proper sleep state as determined by the operating system and software. If the power button is pressed and held for four seconds, the system powers off (S5 state). This feature is called power button override and is particularly helpful in case of system hang and system lock. The power button is located next to the SATA connectors on the board.

4.2Sleep States Supported

The I/O controller controls the system sleep states. States S0, S1, S3, and S5 are supported. The platform enters sleep states in response to BIOS, operating system, or user actions. Normally the operating system determines which sleep state to transition into. However, a four second power button override event places the system immediately into S5. When transitioning into a software-invoked sleep state, the I/O controller attempts to gracefully put the system to sleep by first going into the processor C2 state.

4.2.1S0 State

This is the normal operating state, even though there are some power savings modes in this state using processor Halt and Stop Clock (processor C1 and C2 states). S0 affords the fastest wake-up response time of any sleep state because the system remains fully powered and memory is intact.

4.2.2S1 State

This state is entered via a processor Sleep signal from the I/O controller (processor C3 state). The system remains fully powered with memory contents intact but the processors enter their lowest power state. The operating system disables bus masters for uniprocessor configurations while flushing and invalidating caches before entering this state in multiprocessor configurations. Wake-up latency is slightly longer in this state than in S0; however, power savings are improved from S0.

4.2.3S2 State

This state is not supported.

4.2.4S3 State

This state is called Suspend to RAM (STR). The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop except the RTC. S3 is entered when the I/O controller asserts the SLP_S3# signal to downstream circuitry to control 1.8 V power plane switching.

	Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH
April 2007	User’s Manual
Order Number: 311274-009	37