
| 4.1 | Power Button | 37 | |
| 4.2 | Sleep States Supported | 37 | |
|
| 4.2.1 | S0 State | 37 |
|
| 4.2.2 | S1 State | 37 |
|
| 4.2.3 | S2 State | 37 |
|
| 4.2.4 | S3 State | 37 |
|
| 4.2.5 | S4 State | 38 |
|
| 4.2.6 | S5 State | 38 |
|
| 4.2.7 | 38 | |
|
| 4.2.8 | Wake from S1 Sleep State | 38 |
|
| 4.2.9 | Wake from S3 State | 38 |
|
| 4.2.10 | Wake from S5 State | 39 |
| 4.3 | PCI PM Support | 39 | |
| 4.4 | Platform Management | 39 | |
|
| 4.4.1 | Processor Thermal Management | 39 |
| 4.5 | System Fan Operation | 39 | |
5.0 Driver and OS Support | 40 | |||
6.0 | Hardware Reference | 41 | ||
| 6.1 | Chipset Components | 42 | |
| 6.2 | Expansion Slots and Sockets | 42 | |
|
| 6.2.1 | PCI Express* Connector | 42 |
|
| 6.2.2 | 44 | |
|
| 6.2.3 | 45 | |
|
| 6.2.4 | Processor Sockets | 48 |
|
| 6.2.5 | Firmware Hub (FWH) BIOS Socket | 48 |
|
| 6.2.6 | Battery | 48 |
| 6.3 | 48 | ||
|
| 6.3.1 | SATA Connector | 49 |
|
| 6.3.2 | IDE Connector | 49 |
|
| 6.3.3 | Floppy Drive Connector | 50 |
|
| 6.3.4 | Front Panel Connector | 50 |
| 6.4 | Jumpers | 51 | |
| 6.5 | SMBUS Headers | 53 | |
| 6.6 | Back Panel Connectors | 53 | |
|
| 6.6.1 | 53 | |
|
| 6.6.2 | Parallel Port | 53 |
|
| 6.6.3 | Serial Ports | 54 |
|
| 6.6.4 | Dual Stacked USB Connectors | 54 |
|
| 6.6.5 | Video Port | 55 |
7.0 | Board Setup Checklist | 56 | ||
8.0 | Debug Procedure | 57 | ||
| 8.1 | Level 1 Debug (Port80/BIOS) | 57 | |
| 8.2 | Level 2 Debug (Power Sequence) | 57 | |
| 8.3 | Level 3 Debug (Voltage References) | 58 |
Figures
1 | Board before Installing Additional Hardware | 14 |
2 | Location for the CPU and MCH for Heatsink Installation | 16 |
3 | CPU Heatsink Top and Bottom View | 17 |
4 | Processor in Socket and Package Secured | 17 |
5 | Clean Top of Processor Die | 18 |
| ||
User’s Manual | April 2007 | |
4 |
| Order Number: |