
Figure 16. Power Distribution Block Diagram
|
|
| DDR | DIMMS |
12V |
|
| 1.8 V | |
|
| 50 A |
| |
18A |
|
|
|
|
|
|
| DDR |
|
|
|
| S3 | S3_CNTRL |
|
|
| Switch |
|
VCCP 0 | VCCP 1 |
|
| |
1A |
|
| ||
| 50 A | 50 A |
|
|
| VRM 11 |
|
|
|
5.0V |
|
|
|
|
50A |
|
|
|
|
| 1.5V |
|
|
|
| 13 A |
|
|
|
|
|
| VCCP |
|
|
| 1.05 V |
| |
|
| 6.0 A |
| |
0.5A |
|
|
|
|
|
| 1.8VDDRSB |
|
|
5.0VSTBY |
| 3 A |
|
|
|
|
|
| |
2.5A |
|
|
|
|
|
| 3.3VSTBY | 1.5VSTBY |
|
|
| 3.0 A | 0.8 A |
|
3.3V |
| 3.3 AUX |
|
|
28A |
|
|
| |
|
| 1.7 A |
|
|
450W ATX |
|
|
|
|
3.3.10Clock Generation
The CRB uses one CK409B Clock Synthesizer to generate the host differential pair clocks and the 100MHz differential clock to the DB800. The DB800 then generates the 100 MHz differential pair clock for the PCI Express devices. Figure 17 shows the CRB clock configuration.
| |
April 2007 | User’s Manual |
Order Number: | 31 |