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Intel® IQ80219 General Purpose PCI Processor Evaluation Platform IQ80310 and IQ80219 Comparisons

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86	Board Manual

Image 86

Intel IQ80219 manual This Page Left Intentionally Blank

Contents

Board Manual November 13 Board Manual Contents Debug Interface Dram Exploring the CodeLab Debug Windows 100 119 Figures Rstmode and Retry Operation Setting Summary Tables 105 Revision History Date Revision Description This Page Left Intentionally Blank Document Purpose and Scope Related Documents Electronic Information Electronic InformationComponent References Component Reference Definition Terms and DefinitionsTerms and Definitions Intel 80219 General Purpose PCI Processor Block Diagram Intel 80219 General Purpose PCI Processor Introduction Feature Definition Intel IQ80219 Evaluation Platform Board FeaturesSummary of Features First-Time Installation and Test Kit ContentHardware Installation Power and Backplane Requirements Development Strategy Factory SettingsContents of the Flash Supported Tool Buckets Redhat Redboot Target Monitors ARM Firmware Suite ARM Angel Semihosting File I/O Ethernet-Network Communication Host Communications ExamplesSerial-UART Communication Jtag Debug Communication Jtag Debug Communication Communicating with Redboot GNUPro GDB/Insight Getting Started Connecting with GDB GDB set remotebaud ARM Extended Debugger This Page Left Intentionally Blank Giga Ethernet Functional DiagramIntel ﬁ Bridge Form-Factor/Connectivity Features Board Form-Factor/Connectivity Power Power Features Memory Subsystem Battery BackupDDR Memory Features Supported Dimm Types Flash Memory Requirements Flash Memory Requirements Intel 80219 General Purpose PCI Processor Operation Mode Interrupt Routing IQ80219 Interrupt routing Peripheral Bus Features Intel IQ80219 Evaluation Platform Board Peripheral Bus Flash ROM Features Flash ROM Uart Features Uart HEX Display HEX Display on the Peripheral Bus Rotary Switch Rotary Switch Requirements Battery Status Battery Status Buffer Requirements Ethernet Port Debug InterfaceConsole Serial Port Intel 82544EI Gigabit Ethernet Controller 3.1 Jtag Port Logic-Analyzer ConnectorsJtag Debug Jtag Port Pin-out Micor J3F2 Signal/Pins Mictor J3F2 Mictor J2F1 Micor J2F1 Signal/PinsSchematic Signal Name Micor J1C1 Signal/Pins Mictor J1C1 Micor J3C1 Signal/Pins Mictor J3C1 Micor J2C1 Signal/Pins Mictor J2C1 Board Reset Scheme Reset Requirements/Schemes Switches and Jumpers Switch Summary Pcix Initialization Summary User Defined SwitchesPCI-X Bridge Initialization Signals Default Switch Settings Visual General Purpose Input/Output Header Connector SummaryJumper Summary Primary PCI/PCI-X Operation Settings Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation Mode Detail Descriptions of Switches/Jumpers Switch S7E1- 2/3 Switch S7E1- 4/5 Switch S7E1- 6/7 Switch S7E1 8 Settings and Operation Mode Switch S7E1Switch S7E1 8 Descriptions S7E1-8 Switch S8E1 Switch S8E1 5 Driver Mode Output Impedances Switch S8E1 5 DescriptionsSwitch S8E1 5 Settings and Operation Mode Switch S8E1 6 Descriptions Switch S8E1 8 Descriptions Switch S8E1 7 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 8 Settings and Operation Mode Switch S8E2 1/2 Switch S8E2 Switch S9E1 13 Settings and Operation Mode Switch S9E1Switch S9E1 13 Descriptions Switch S9E1 4 Descriptions Switch S4D1 3/4 Switch S1D1 1/2Switch S4D1 1/2 Jumper J3G1 Jumper J1G2Jumper J3E1 Jumper J9E1 Jumper J9F1 This Page Left Intentionally Blank Idsel Routing for Private Device Configuration Private Device ConfigurationPrivate Device Configuration Requirements Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private Device DDR Memory Bias Voltage Minimum/Maximum Values DramComponents on the Peripheral Bus Software Reference Uart Register Settings Address Read Register Write Register Hex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel General Purpose PCI Processor Memory Map Board Support Package BSP ExamplesIntel 80219 General Purpose PCI Processor Memory Map Redboot* Intel IQ80219 Memory Map Physical Address Range Description Redboot Intel IQ80219 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80219 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80219 Files Redboot Intel IQ80219 DDR Memory Initialization Sequence Redboot Switching This Page Left Intentionally Blank IQ80310 and IQ80219 Comparisons This Page Left Intentionally Blank Necessary Hardware and Software IntroductionPurpose Related Web Sites Setup Hardware Setup Software Setup Software Flow Diagram New Project Setup Creating a New Project Configuration Flashing with Jtag Overview Using Flash Programmer Debugging Out of Flash Building an Executable File From Example Code Launching and Configuring Debugger Running the CodeLab Debugger Manually Loading and Executing an Application Program Displaying Source Code Using Breakpoints Setting CodeLab Debug Options Stepping Through the Code Exploring the CodeLab Debug Windows Variables Window Registers WindowWatch Window Software Breakpoints Debugging BasicsHardware and Software Breakpoints Hardware Breakpoints Exceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping