Intel IXP2800 3.6.2.4 Round-Robin Replacement Algorithm, 3.6.2.5 Parity Protection, 3.6.2.6 Atomic Accesses

102 Hardware Reference Manual
Intel® IXP2800 Network Processor
Intel XScale® Core
3.6.2.4 Round-Robin Replacement Algorithm
The line replacement algorithm for the data cache is round-robin. Each set in the data cache has a
round-robin pointer that keeps track of the next line (in that set) to replace. The next line to replace
in a set is the next sequential line after the last one that was just filled. For example, if the line for
the last fill was written into way5-set 2, the next line to replace for that set would be way 6. None
of the other round-robin pointers for the other sets are affected in this case.
After reset, way3 1 is pointed to by the round-robin pointer for all the sets. Once a line is written
into way 31, the round-robin pointer points to the first available way of a set, beginning with way 0
if no lines have been reconfigured as data RAM in that particular set. Reconfiguring lines as data
RAM effectively reduces the available lines for cache updating. For example, if the first three lines
of a set were reconfigured, the round-robin pointer would point to the line at way 3 after it rolled
over from way 31. Refer to Section 3.6.4 for more details on data RAM.
The mini-data cache follows the same round-robin replacement algorithm as the data cache except
that there are only two lines the round-robin pointer can point to such that the round-robin pointer
always points to the least recently filled line. A least recently used replacement algorithm is not
supported because the purpose of the mini-data cache is to cache data that exhibits low temporal
locality, i.e., data that is placed into the mini-data cache is typically modified once and then written
back out to external memory.
3.6.2.5 Parity Protection
The data cache and mini-data cache are protected by parity to ensure data integrity; there is one
parity bit per byte of data. (The tags are not parity protected.) When a parity error is detected on a
data/mini-data cache access, a data abort exception occurs. Before servicing the exception,
hardware will set bit 10 of the Fault Status register.
A data/mini-data cache parity error is an imprecise data abort, meaning R14_ABORT (+8) may not
point to the instruction that caused the parity error. If the parity error occurred during a load, the
targeted register may be updated with incorrect data.
A data abort due to a data/mini-data cache parity error may not be recoverable if the data address
that caused the abort occurred on a line in the cache that has a write-back caching policy. Prior
updates to this line may be lost; in this case the software exception handler should perform a “clean
and clear” operation on the data cache, ignoring subsequent parity errors, and restart the offending
process. This operation is shown in Section 3.6.3.3.1.
3.6.2.6 Atomic Accesses
The SWP and SWPB instructions generate an atomic load and store operation allowing a memory
semaphore to be loaded and altered without interruption. These accesses may hit or miss the data/
mini-data cache depending on configuration of the cache, configuration of the MMU, and the page
attributes. Refer to Section 3.11.4 for more information.