Main
2Hardware Reference Manual
Revision History
Contents
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Figures
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Tables
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Introduction 1
1.1 About This Document
1.2 Related Documentation
1.3 Terminology
Technical Description 2
2.1 Overview
Intel IXP2800 Network Processor
Figure 1. IXP2800 Network Processor Functional Block Diagram
Figure 2. IXP2800 Network Processor Detailed Diagram
2.2 Intel XScale Core Microarchitecture
2.2.1 ARM* Compatibility
2.2.2 Features
2.2.2.1 Multiply/Accumulate (MAC)
2.2.2.2 Memory Management
2.2.2.4 Branch Target Buffer
2.2.2.5 Data Cache
2.2.2.6 Interrupt Controller
2.2.2.7 Address Map
2.3 Microengines
Figure 4. Microengine Block Diagram
NNData_In (from previous ME)
D_Push (from DRAM)
S_Push (from SRAM Scratchpad, MSF, Hash, PCI, CAP)
Control Store
2.3.1 Microengine Bus Arrangement
2.3.2 Control Store
2.3.3 Contexts
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2.3.4 Datapath Registers
2.3.4.1 General-Purpose Registers (GPRs)
2.3.4.2 Transfer Registers
2.3.4.3 Next Neighbor Registers
2.3.4.4 Local Memory
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2.3.5 Addressing Modes
2.3.5.1 Context-Relative Addressing Mode
2.3.5.2 Absolute Addressing Mode
2.3.5.3 Indexed Addressing Mode
2.3.6 Local CSRs
2.3.7 Execution Datapath
2.3.7.1 Byte Align
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2.3.7.2 CAM
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2.3.8 CRC Unit
2.3.9 Event Signals
2.4 DRAM
2.4.1 Size Configuration
2.4.2 Read and Write Access
2.5 SRAM
2.5.1 QDR Clocking Scheme
2.5.2 SRAM Controller Configurations
2.5.3 SRAM Atomic Operations
2.5.4 Queue Data Structure Commands
2.5.5 Reference Ordering
Table 12. Address Reference Order
Table 13. Q_array Entry Reference Order
2.5.5.2 Microengine Software Restrictions to Maintain Ordering
2.6 Scratchpad Memory
2.6.1 Scratchpad Atomic Operations
2.6.2 Ring Commands
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2.7 Media and Switch Fabric Interface
2.7.1 SPI-4
2.7.2 CSIX
2.7.3 Receive
2.7.3.1 RBUF
2.7.3.2 Full Element List
2.7.3.3 RX_THREAD_FREELIST
2.7.3.4 Receive Operation Summary
2.7.4 Transmit
2.7.4.1 TBUF
The definitions of the fields are shown in Table15.
Table 15. TBUF SPI-4 Control Definition
Hardware Reference Manual 67
The definitions of the fields are shown in Table16.
2.7.4.2 Transmit Operation Summary
Table 16. TBUF CSIX Control Definition
2.7.5 The Flow Control Interface
2.7.5.1 SPI-4
2.7.5.2 CSIX
2.8 Hash Unit
Figure 14. Hash Unit Block Diagram
2.9 PCI Controller
2.9.1 Target Access
2.9.2 Master Access
2.9.3 DMA Channels
2.9.3.1 DMA Descriptor
2.9.3.2 DMA Channel Operation
2.9.3.3 DMA Channel End Operation
2.9.3.4 Adding Descriptors to an Unterminated Chain
2.9.4 Mailbox and Message Registers
2.9.5 PCI Arbiter
2.10 Control and Status Register Access Proxy
2.11 Intel XScale Core Peripherals
2.11.1 Interrupt Controller
2.11.2 Timers
2.11.3 General Purpose I/O
2.11.4 Universal Asynchronous Receiver/Transmitter
2.11.5 Slowport
2.12 I/O Latency
2.13 Performance Monitor
Intel XScale Core 3
3.1 Introduction
3.2 Features
3.2.1 Multiply/ACcumulate (MAC)
3.2.2 Memory Management
3.2.3 Instruction Cache
3.2.4 Branch Target Buffer (BTB)
3.2.5 Data Cache
3.2.6 Performance Monitoring
3.2.7 Power Management
3.3 Memory Management
3.3.1 Architecture Model
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3.3.2 Exceptions
3.3.3 Interaction of the MMU, Instruction Cache, and Data Cache
3.3.4 Control
3.3.4.1 Invalidate (Flush) Operation
3.3.4.2 Enabling/Disabling
3.3.4.3 Locking Entries
3.3.4.4 Round-Robin Replacement Algorithm
3.4 Instruction Cache
3.4.1 Instruction Cache Operation
3.4.1.1 Operation when Instruction Cache is Enabled
3.4.1.2 Operation when Instruction Cache is Disabled
3.4.1.3 Fetch Policy
3.4.1.4 Round-Robin Replacement Algorithm
3.4.1.5 Parity Protection
3.4.1.6 Instruction Cache Coherency
3.4.2 Instruction Cache Control
3.4.2.1 Instruction Cache State at Reset
3.4.2.2 Enabling/Disabling
3.4.2.3 Invalidating the Instruction Cache
3.4.2.4 Locking Instructions in the Instruction Cache
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3.4.2.5 Unlocking Instructions in the Instruction Cache
3.5 Branch Target Buffer (BTB)
3.5.1 Branch Target Buffer Operation
3.5.1.1 Reset
SN WN WT ST
3.5.2 Update Policy
3.5.3 BTB Control
3.6 Data Cache
3.6.1 Overviews
3.6.1.1 Data Cache Overview
3.6.1.2 Mini-Data Cache Overview
3.6.1.3 Write Buffer and Fill Buffer Overview
3.6.2 Data Cache and Mini-Data Cache Operation
3.6.2.1 Operation when Caching is Enabled
3.6.2.2 Operation when Data Caching is Disabled
3.6.2.3 Cache Policies
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3.6.2.4 Round-Robin Replacement Algorithm
3.6.2.5 Parity Protection
3.6.2.6 Atomic Accesses
3.6.3 Data Cache and Mini-Data Cache Control
3.6.3.1 Data Memory State After Reset
3.6.3.2 Enabling/Disabling
3.6.3.3 Invalidate and Clean Operations
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3.6.4 Reconfiguring the Data Cache as Data RAM
3.6.5 Write Buffer/Fill Buffer Operation and Control
3.7 Configuration
3.8 Performance Monitoring
3.8.1 Performance Monitoring Events
3.8.1.1 Instruction Cache Efficiency Mode
3.8.1.2 Data Cache Efficiency Mode
3.8.1.3 Instruction Fetch Latency Mode
3.8.1.4 Data/Bus Request Buffer Full Mode
3.8.1.5 Stall/Writeback Statistics
3.8.1.6 Instruction TLB Efficiency Mode
3.9 Performance Considerations
3.9.1 Interrupt Latency
3.9.2 Branch Prediction
3.9.3 Addressing Modes
3.9.4 Instruction Latencies
3.9.4.1 Performance Terms
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3.9.4.2 Branch Instruction Timings
3.9.4.3 Data Processing Instruction Timings
Table 28. Branch Instruction Timings (Predicted by the BTB)
Table 29. Branch Instruction Timings (Not Predicted by the BTB)
Table 30. Data Processing Instruction Timings
3.9.4.4 Multiply Instruction Timings
Table 31. Multiply Instruction Timings (Sheet 1 of 2)
3.9.4.5 Saturated Arithmetic Instructions
Table 32. Multiply Implicit Accumulate Instruction Timings
Table 33. Implicit Accumulator Access Instruction Timings
Table 34. Saturated Data Processing Instruction Timings
Table 31. Multiply Instruction Timings (Sheet 2 of 2)
3.9.4.6 Status Register Access Instructions
3.9.4.7 Load/Store Instructions
3.9.4.8 Semaphore Instructions
Table 35. Status Register Access Instruction Timings
Table 36. Load and Store Instruction Timings
3.10 Test Features
3.10.1 IXP2800 Network Processor Endianness
3.10.1.1 Read and Write Transactions Initiated by the Intel XScale Core
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3.11 Intel XScale Core Gasket Unit
3.11.1 Overview
Figure 26. Intel XScale Core-Initiated Write to the IXP2800 Network Processor (Continued)
Word Write by Intel XScale Core
Network Processor
3.11.2 Intel XScale Core Gasket Functional Description
3.11.2.1 Command Memory Bus to Command Push/Pull Conversion
3.11.3 CAM Operation
3.11.4 Atomic Operations
3.11.4.1 Summary of Rules for the Atomic Command Regarding I/O
3.11.4.2 Intel XScale Core Access to SRAM Q-Array
3.11.5 I/O Transaction
3.11.6 Hash Access
3.11.7 Gasket Local CSR
3.11.8 Interrupt
Figure 29. Interrupt Mask Block Diagram
3.12 Intel XScale Core Peripheral Interface
3.12.1 XPI Overview
3.12.1.1 Data Transfers
3.12.1.2 Data Alignment
3.12.1.3 Address Spaces for XPI Internal Devices
Table 5 3 shows the address space assignment for XPI devices.
Table 52. Data Transaction Alignment
Table 53. Address Spaces for XPI Internal Devices
3.12.2 UART Overview
3.12.3 UART Operation
3.12.3.1 UART FIFO OPERATION
3.12.4 Baud Rate Generator
3.12.5 General Purpose I/O (GPIO)
3.12.6 Timers
3.12.6.1 Timer Operation
3.12.7 Slowport Unit
3.12.7.1 PROM Device Support
3.12.7.2 Microprocessor Interface Support for the Framer
3.12.7.3 Slowport Unit Interfaces
Figure 35 shows the Slowport unit interface diagram.
Table 55. SONET/SDH Devices (Sheet 2 of 2)
Figure 35. Slowport Unit Interface Diagram
3.12.7.4 Address Space
3.12.7.5 Slowport Interfacing Topology
3.12.7.6 Slowport 8-Bit Device Bus Protocols
Figure 37. Slowport Example Application Topology
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3.12.7.7 SONET/SDH Microprocessor Access Support
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Figure 42. An Interface Topology with Lucent* TDAT042G5 SONET/SDH
Lucent TDAT042G5*
Intel IXP2000
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Intel IXP2800
PMC-Sierra* PM5351
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Figure 49. Mode 3 Second Interface Topology with Intel / AMCC* SONET/SDH Device
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Figure 53. Second Interface Topology with Intel / AMCC* SONET/SDH Device
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Microengines 4
4.1 Overview
Figure 56. Microengine Block Diagram
NNData_In (from previous ME)
D_Push (from DRAM)
S_Push (from SRAM Scratchpad, MSF, Hash, PCI, CAP)
Control Store
4.1.1 Control Store
4.1.2 Contexts
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4.1.3 Datapath Registers
4.1.3.3 Next Neighbor Registers
4.1.3.4 Local Memory
4.1.4 Addressing Modes
4.1.4.1 Context-Relative Addressing Mode
4.1.4.2 Absolute Addressing Mode
4.1.4.3 Indexed Addressing Mode
4.2 Local CSRs
4.3 Execution Datapath
4.3.1 Byte Align
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4.3.2 CAM
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4.4 CRC Unit
4.5 Event Signals
4.5.1 Microengine Endianness
4.5.1.2 Write to TBUF
4.5.1.3 Read/Write from/to SRAM
4.5.1.4 Read/Write from/to DRAM
4.5.1.5 Read/Write from/to SHaC and Other CSRs
4.5.1.6 Write to Hash Unit
4.5.2 Media Access
4.5.2.1 Read from RBUF
4.5.2.2 Write to TBUF
4.5.2.3 TBUF to SPI-4 Transfer
DRAM 5
5.1 Overview
5.2 Size Configuration
5.3 DRAM Clocking
DRAM
5.4 Bank Policy
Figure 67. IXP2800 Clocking for RDRAM at 400 MHz
RMC RAC
System Ref_Clk
DRCG
5.5 Interleaving
5.5.1 Three Channels Active (3-Way Interleave)
DRAM Table 63. Address Rearrangement for 3-Way Interleave (Sheet 1 of 2)
5.5.2 Two Channels Active (2-Way Interleave)
5.5.3 One Channel Active (No Interleave)
5.5.4 Interleaving Across RDRAMs and Banks
5.6 Parity and ECC
5.6.1 Parity and ECC Disabled
5.6.2 Parity Enabled
5.6.3 ECC Enabled
5.6.4 ECC Calculation and Syndrome
5.7 Timing Configuration
5.8 Microengine Signals
5.9 Serial Port
5.10 RDRAM Controller Block Diagram
5.10.1 Commands
5.10.2 DRAM Write
5.10.2.1 Masked Write
5.10.3 DRAM Read
5.10.4 CSR Write
5.10.5 CSR Read
5.10.6 Arbitration
5.11 DRAM Push/Pull Arbiter
5.11.1 Arbiter Push/Pull Operation
5.11.2 DRAM Push Arbiter Description
5.12 DRAM Pull Arbiter Description
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SRAM Interface 6
6.1 Overview
6.2 SRAM Interface Configurations
6.2.1 Internal Interface
6.2.2 Number of Channels
6.2.3 Coprocessor and/or SRAMs Attached to a Channel
6.3 SRAM Controller Configurations
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6.4 Command Overview
6.4.1 Basic Read/Write Commands
6.4.2 Atomic Operations
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6.4.3 Queue Data Structure Commands
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6.4.3.1 Read_Q_Descriptor Commands
6.4.3.2 Write_Q_Descriptor Commands
6.4.3.3 ENQ and DEQ Commands
6.4.4 Ring Data Structure Commands
6.4.5 Journaling Commands
6.5 Parity
6.6 Address Map
6.7 Reference Ordering
6.7.1 Reference Order Tables
SRAM Interface
6.7.2 Microcode Restrictions to Maintain Ordering
Table 78. Q_array Entry Reference Order
Example 31. Table Update Microcode
6.8 Coprocessor Mode
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SHaC Unit Expansion 7
7.1 Overview
7.1.1 SHaC Unit Block Diagram
Figure 84. SHaC Top Level Diagram
7.1.2 Scratchpad
7.1.2.1 Scratchpad Description
Figure 85. Scratchpad Block Diagram
Scratchpad State Machine
Scratchpad RAM
7.1.2.2 Scratchpad Interface
7.1.2.3 Scratchpad Block Level Diagram
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Writes
Reads
Signal Done
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7.1.3 Hash Unit
Hash Algorithm
HASH_RESULT
7.1.3.1 Hashing Operation
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7.1.3.2 Hash Algorithm
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Media and Switch Fabric Interface 8
8.1 Overview
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8.1.1 SPI-4
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Table84 shows the order of bytes on SPI-4; this example shows a 43-byte packet.
Table 84. Order of Bytes1 within the SPI-4 Data Burst
Figure 90. Receive and Transmit Clock Generation
8.1.2 CSIX
8.1.3 CSIX/SPI-4 Interleave Mode
8.2 Receive
The receive section consists of:
8.2.1 Receive Pins
8.2.2 RBUF
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8.2.2.1 SPI-4
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The status contains the following information:
The definitions of the fields are shown in Table90.
Table 90. RBUF SPIF-4 Status Definition
8.2.2.2 CSIX
The definitions of the fields are shown in Table91.
Table 91. RBUF CSIX Status Definition
8.2.3 Full Element List
8.2.4 Rx_Thread_Freelist_#
8.2.5 Rx_Thread_Freelist_Timeout_#
8.2.6 Receive Operation Summary
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8.2.7 Receive Flow Control Status
8.2.7.1 SPI-4
8.2.7.2 CSIX
8.2.8 Parity
8.2.8.1 SPI-4
8.2.8.2 CSIX
8.2.9 Error Cases
8.3 Transmit
The transmit section consists of:
Each of these is described below. Figure 94 is a simplified block diagram of the MSF transmit block.
8.3.1 Transmit Pins
8.3.2 TBUF
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8.3.2.1 SPI-4
The definitions of the fields are shown in Table98.
Table 98. TBUF SPI-4 Control Definition
8.3.2.2 CSIX
The definitions of the fields are shown in Table99.
Table 99. TBUF CSIX Control Definition
8.3.3 Transmit Operation Summary
8.3.3.1 SPI-4
8.3.3.2 CSIX
8.3.3.3 Transmit Summary
8.3.4 Transmit Flow Control Status
8.3.4.1 SPI-4
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8.3.4.2 CSIX
8.3.5 Parity
8.3.5.1 SPI-4
8.3.5.2 CSIX
8.4 RBUF and TBUF Summary
8.5 CSIX Flow Control Interface
8.5.1 TXCSRB and RXCSRB Signals
8.5.2 FCIFIFO and FCEFIFO Buffers
8.5.2.1 Full Duplex CSIX
8.5.2.2 Simplex CSIX
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8.5.3 TXCDAT/RXCDAT, TXCSOF/RXCSOF, TXCPAR/RXCPAR, and TXCFC/RXCFC Signals
8.6 Deskew and Training
Table 105. Calendar Deskew Functions
Table 106. Flow Control Deskew Functions
8.6.1 Data Training Pattern
8.6.2 Flow Control Training Pattern
8.6.3 Use of Dynamic Training
Table 110. IXP2800 Network Processor Requires Data Training
Table 111. Switch Fabric or SPI-4 Framer Requires Data Training
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8.7 CSIX Startup Sequence
8.7.1 CSIX Full Duplex
8.7.1.1 Ingress IXP2800 Network Processor
8.7.1.2 Egress IXP2800 Network Processor
8.7.1.3 Single IXP2800 Network Processor
8.7.2 CSIX Simplex
8.7.2.1 Ingress IXP2800 Network Processor
8.7.2.2 Egress IXP2800 Network Processor
8.7.2.3 Single IXP2800 Network Processor
8.8 Interface to Command and Push and Pull Buses
Figure 100. MSF to Command and Push and Pull Buses Interface Block Diagram
TBUF
RBUF
8.8.1 RBUF or MSF CSR to Microengine S_TRANSFER_IN Register for Instruction:
8.8.2 Microengine S_TRANSFER_OUT Register to TBUF or MSF CSR for Instruction:
8.8.3 Microengine to MSF CSR for Instruction:
8.8.4 From RBUF to DRAM for Instruction:
8.8.5 From DRAM to TBUF for Instruction:
8.9 Receiver and Transmitter Interoperation with Framers and Switch Fabrics
8.9.1 Receiver and Transmitter Configurations
Receiver
Transmitter
8.9.1.2 Hybrid Simplex Configuration
Processor
Network
Transmitter Fabric Receiver
8.9.1.3 Dual Network Processor Full Duplex Configuration
8.9.1.4 Single Network Processor Full Duplex Configuration (SPI-4.2)
8.9.1.5 Single Network Processor, Full Duplex Configuration (SPI-4.2 and CSIX-L1)
8.9.2 System Configurations
8.9.2.1 Framer, Single Network Processor Ingress and Egress, and Fabric Interface Chip
Figure 107. Framer, Single Network Processor Ingress and Egress, and Fabric Interface Chip
Figure 108. Framer, Dual Processor Ingress, Single Processor Egress, and Fabric Interface Chip
8.9.2.4 CPU Complex, Network Processor, and Fabric Interface Chip
8.9.2.5 Framer, Single Network Processor, Co-Processor, and Fabric Interface Chip
8.9.3 SPI-4.2 Support
8.9.3.1 SPI-4.2 Receiver
8.9.3.2 SPI-4.2 Transmitter
8.9.4 CSIX-L1 Protocol Support
8.9.4.1 CSIX-L1 Interface Reference Model: Traffic Manager and Fabric Interface Chip
8.9.4.2 Intel IXP2800 Support of the CSIX-L1 Protocol
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8.9.4.3 CSIX-L1 Protocol Receiver Support
8.9.4.4 CSIX-L1 Protocol Transmitter Support
8.9.4.5 Implementation of a Bridge Chip to CSIX-L1
8.9.5 Dual Protocol (SPI and CSIX-L1) Support
8.9.5.1 Dual Protocol Receiver Support
8.9.5.2 Dual Protocol Transmitter Support
8.9.5.3 Implementation of a Bridge Chip to CSIX-L1 and SPI-4.2
8.9.6 Transmit State Machine
8.9.6.1 SPI-4.2 Transmitter State Machine
8.9.6.2 Training Transmitter State Machine
8.9.6.3 CSIX-L1 Transmitter State Machine
8.9.7 Dynamic De-Skew
8.9.8 Summary of Receiver and Transmitter Signals
Intel IXP2800 Network Processor
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PCI Unit 9
9.1 Overview
Figure 118. PCI Functional Blocks
64-bit PCI Bus
Command Bus Master
Command Bus Slave
Master Interface
9.2 PCI Pin Protocol Interface Block
9.2.1 PCI Commands
9.2.2 IXP2800 Network Processor Initialization
9.2.2.1 Initialization by the Intel XScale Core
9.2.2.2 Initialization by a PCI Host
9.2.3 PCI Type 0 Configuration Cycles
9.2.3.1 Configuration Write
9.2.3.2 Configuration Read
9.2.4 PCI 64-Bit Bus Extension
9.2.5 PCI Target Cycles
9.2.5.5 Target Read Accesses from the PCI Bus
9.2.6 PCI Initiator Transactions
9.2.6.1 PCI Request Operation
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9.2.6.6 Special Cycle
9.2.7 PCI Fast Back-to-Back Cycles
9.2.8 PCI Retry
9.2.9 PCI Disconnect
9.2.11 PCI Central Functions
9.2.11.1 PCI Interrupt Inputs
9.2.11.2 PCI Reset Output
9.2.11.3 PCI Internal Arbiter
9.3 Slave Interface Block
9.3.1 CSR Interface
9.3.2 SRAM Interface
9.3.2.1 SRAM Slave Writes
9.3.2.2 SRAM Slave Reads
9.3.3 DRAM Interface
9.3.3.1 DRAM Slave Writes
9.3.3.2 DRAM Slave Reads
9.3.4 Mailbox and Doorbell Registers
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9.3.5 PCI Interrupt Pin
An external PCI interrupt can be generated in the following way:
Figure 126 shows how PCI interrupts are managed via the PCI and the Intel XScale core.
Table125 describes how IRQ are generated for each silicon stepping.
9.4 Master Interface Block
9.4.1 DMA Interface
9.4.1.1 Allocation of the DMA Channels
9.4.1.2 Special Registers for Microengine Channels
9.4.1.3 DMA Descriptor
9.4.1.4 DMA Channel Operation
9.4.1.5 DMA Channel End Operation
9.4.1.6 Adding Descriptor to an Unterminated Chain
9.4.1.7 DRAM to PCI Transfer
9.4.1.8 PCI to DRAM Transfer
9.4.2 Push/Pull Command Bus Target Interface
9.4.2.1 Command Bus Master Access to Local Configuration Registers
9.4.2.2 Command Bus Master Access to Local Control and Status Registers
9.4.2.3 Command Bus Master Direct Access to PCI Bus
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9.5 PCI Unit Error Behavior
9.5.1 PCI Target Error Behavior
9.5.2 As a PCI Initiator During a DMA Transfer
9.5.2.2 DMA Read from SRAM (Descriptor Read) Gets a Memory Error
9.5.2.3 DMA from DRAM Transfer (Write to PCI) Receives PCI_PERR_L on PCI Bus
9.5.2.4 DMA To DRAM (Read from PCI) Has Bad Data Parity
9.5.2.5 DMA Transfer Experiences a Master Abort (Time-Out) on PCI
9.5.2.6 DMA Transfer Receives a Target Abort Response During a Data Phase
9.5.3 As a PCI Initiator During a Direct Access from the Intel XScale Core or Microengine
9.5.3.1 Master Transfer Experiences a Master Abort (Time-Out) on PCI
9.5.3.2 Master Transfer Receives a Target Abort Response During a Data Phase
9.5.3.4 Master Read from PCI (Read from PCI) Has Bad Data Parity
9.5.3.5 Master Transfer Receives PCI_SERR_L from the PCI Bus
9.6 PCI Data Byte Lane Alignment
PCI Data SRAM Data
Table 131. Byte Lane Alignment for 64-Bit PCI Data In (64 Bits PCI Big-Endian to Big-Endian
PCI Data SRAM Data
PCI Add[2]=1 PCI Add[2]=0
PCI Data SRAM Data
Table 133. Byte Lane Alignment for 32-Bit PCI Data In (32 Bits PCI Big-Endian to Big-Endian
Table 134. Byte Lane Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI Little
Table 135. Byte Lane Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI Big-Endian
Table 136. Byte Lane Alignment for 32-Bit PCI Data Out (Big-Endian to 32 Bits PCI Little
Table 137. Byte Lane Alignment for 32-Bit PCI Data Out (Big-Endian to 32 Bits PCI Big-Endian
9.6.1 Endian for Byte Enable
Table 141. Byte Enable Alignment for 32-Bit PCI Data In (32 Bits PCI Big-Endian to Big-Endian
Table 142. Byte Enable Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI Little
PCI Add[2]=1 PCI Add[2]=0
SRAM Data
PCI Side
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Table 146. PCI I/O Cycles with Data Swap Enable Stepping Description
Clocks and Reset 10
10.1 Clocks
Figure 130. Overall Clock Generation and Distribution
Clock Unit with PLL
Intel IXP2800 Network Processor
Table 147. Clock Usage Summary (Sheet 1 of 2)
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Table 148. Clock Rates Examples
10.2 Synchronization Between Frequency Domains
10.3 Reset
10.3.1 Hardware Reset Using nRESET or PCI_RST_L
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10.3.2 PCI-Initiated Reset
10.3.3 Watchdog Timer-Initiated Reset
10.3.4 Software-Initiated Reset
10.3.5 Reset Removal Operation Based on CFG_PROM_BOOT
10.3.5.1 When CFG_PROM_BOOT is 1 (BOOT_PROM is Present)
10.3.5.2 When CFG_PROM_BOOT is 0 (BOOT_PROM is Not Present)
10.3.6 Strap Pins
Table 149. IXP2800 Network Processor Strap Pins
10.3.7 Powerup Reset Sequence
10.4 Boot Mode
Figure 135. Boot Process
10.4.1 Flash ROM
10.4.2 PCI Host Download
10.5 Initialization
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Performance Monitor Unit 11
11.1 Introduction
11.1.1 Motivation for Performance Monitors
11.1.2 Motivation for Choosing CHAP Counters
Performance Monitoring Unit
11.1.3 Functional Overview of CHAP Counters
11.1.4 Basic Operation of the Performance Monitor Unit
11.1.5 Definition of CHAP Terminology
Figure 138. Basic Block Diagram of IXP2800 Network Processor with PMU
11.1.6 Definition of Clock Domains
11.2 Interface and CSR Description
11.2. 1 APB P eriph eral
11.2.2 CAP Description
11.2.2.1 Selecting the Access Mode
11.2.2.2 PMU CSR
11.2.2.3 CAP Writes
11.3 Performance Measurements
Table 152. Hardware Blocks and Their Performance Measurement Events (Sheet 1 of 2)
Table 152. Hardware Blocks and Their Performance Measurement Events (Sheet 2 of 2)
11.4 Events Monitored in Hardware
11.4.1 Queue Statistics Events
11.4.1.1 Queue Latency
11.4.1.2 Queue Utilization
11.4.2 Count Events
11.4.3 Design Block Select Definitions
11.4.4 Null Event
Table 153. PMU Design Unit Selection (Sheet 2 of 2)
11.4.5 Threshold Events
11.4.6 External Input Events
11.4.6.1 XPI Events Target ID(000001) / Design Block #(0100)
Table 155. XPI PMU Event List (Sheet 1 of 4)
Table 155. XPI PMU Event List (Sheet 2 of 4)
Table 155. XPI PMU Event List (Sheet 3 of 4)
Table 155. XPI PMU Event List (Sheet 4 of 4)
11.4.6.2 SHaC Events Target ID(000010) / Design Block #(0101)
Table 156. SHaC PMU Event List (Sheet 1 of 4)
Table 156. SHaC PMU Event List (Sheet 2 of 4)
Table 156. SHaC PMU Event List (Sheet 3 of 4)
11.4.6.3 IXP2800 Network Processor MSF Events Target ID(000011) / Design Block #(0110)
Table 156. SHaC PMU Event List (Sheet 4 of 4)
Table 157. IXP2800 Network Processor MSF PMU Event List (Sheet 1 of 6)
Table 157. IXP2800 Network Processor MSF PMU Event List (Sheet 2 of 6)
Table 157. IXP2800 Network Processor MSF PMU Event List (Sheet 3 of 6)
Table 157. IXP2800 Network Processor MSF PMU Event List (Sheet 4 of 6)
Table 157. IXP2800 Network Processor MSF PMU Event List (Sheet 5 of 6)
Table 157. IXP2800 Network Processor MSF PMU Event List (Sheet 6 of 6)
11.4.6.4 Intel XScale Core Events Target ID(000100) / Design Block #(0111)
Table 158. Intel XScale Core Gasket PMU Event List (Sheet 1 of 4)
Table 158. Intel XScale Core Gasket PMU Event List (Sheet 2 of 4)
Table 158. Intel XScale Core Gasket PMU Event List (Sheet 3 of 4)
11.4.6.5 PCI Events Target ID(000101) / Design Block #(1000)
Table 158. Intel XScale Core Gasket PMU Event List (Sheet 4 of 4)
Table 159. PCI PMU Event List (Sheet 1 of 5)
Table 159. PCI PMU Event List (Sheet 2 of 5)
Table 159. PCI PMU Event List (Sheet 3 of 5)
Table 159. PCI PMU Event List (Sheet 4 of 5)
11.4.6.6 ME00 Events Target ID(100000) / Design Block #(1001)
Table 159. PCI PMU Event List (Sheet 5 of 5)
Table 160. ME00 PMU Event List (Sheet 1 of 2)
11.4.6.7 ME01 Events Target ID(100001) / Design Block #(1001)
Table 160. ME00 PMU Event List (Sheet 2 of 2)
Table 161. ME01 PMU Event List
11.4.6.8 ME02 Events Target ID(100010) / Design Block #(1001)
11.4.6.9 ME03 Events Target ID(100011) / Design Block #(1001)
Table 162. ME02 PMU Event List
Table 163. ME03 PMU Event List
11.4.6.10 ME04 Events Target ID(100100) / Design Block #(1001)
11.4.6.11 ME05 Events Target ID(100101) / Design Block #(1001)
Table 164. ME04 PMU Event List
Table 165. ME05 PMU Event List
11.4.6.12 ME06 Events Target ID(100110) / Design Block #(1001)
11.4.6.13 ME07 Events Target ID(100111) / Design Block #(1001)
Table 166. ME06 PMU Event List
Table 167. ME07 PMU Event List
11.4.6.14 ME10 Events Target ID(110000) / Design Block #(1010)
11.4.6.15 ME11 Events Target ID(110001) / Design Block #(1010)
Table 168. ME10 PMU Event List
Table 169. ME11 PMU Event List
11.4.6.16 ME12 Events Target ID(110010) / Design Block #(1010)
11.4.6.17 ME13 Events Target ID(110011) / Design Block #(1010)
Table 170. ME12 PMU Event List
Table 171. ME13 PMU Event List
11.4.6.18 ME14 Events Target ID(110100) / Design Block #(1010)
11.4.6.19 ME15 Events Target ID(110101) / Design Block #(1010)
Table 172. ME14 PMU Event List
Table 173. ME15 PMU Event List
11.4.6.20 ME16 Events Target ID(100110) / Design Block #(1010)
11.4.6.21 ME17 Events Target ID(110111) / Design Block #(1010)
Table 174. ME16 PMU Event List
Table 175. ME17 PMU Event List
11.4.6.22 SRAM DP1 Events Target ID(001001) / Design Block #(0010)
11.4.6.23 SRAM DP0 Events Target ID(001010) / Design Block #(0010)
Table 176. SRAM DP1 PMU Event List
Table 177. SRAM DP0 PMU Event List (Sheet 1 of 3)
Table 177. SRAM DP0 PMU Event List (Sheet 2 of 3)
11.4.6.24 SRAM CH3 Events Target ID(001011) / Design Block #(0010)
Table 177. SRAM DP0 PMU Event List (Sheet 3 of 3)
Table 178. SRAM CH3 PMU Event List
11.4.6.25 SRAM CH2 Events Target ID(001100) / Design Block #(0010)
11.4.6.26 SRAM CH1 Events Target ID(001101) / Design Block #(0010)
Table 179. SRAM CH3 PMU Event List
Table 180. SRAM CH3 PMU Event List
11.4.6.27 SRAM CH0 Events Target ID(001110) / Design Block #(0010)
Table 181. SRAM CH0 PMU Event List (Sheet 1 of 2)
11.4.6.28 DRAM DPLA Events Target ID(010010) / Design Block #(0011)
Table 181. SRAM CH0 PMU Event List (Sheet 2 of 2)
Table 182. IXP2800 Network Processor Dram DPLA PMU Event List (Sheet 1 of 2)
11.4.6.29 DRAM DPSA Events Target ID(010011) / Design Block #(0011)
Table 182. IXP2800 Network Processor Dram DPLA PMU Event List (Sheet 2 of 2)
Table 183. IXP2800 Network Processor Dram DPSA PMU Event List (Sheet 1 of 2)
11.4.6.30 IXP2800 Network Processor DRAM CH2 Events Target ID(010100) /
Table 183. IXP2800 Network Processor Dram DPSA PMU Event List (Sheet 2 of 2)
Table 184. IXP2800 Network Processor Dram CH2 PMU Event List (Sheet 1 of 5)
Table 184. IXP2800 Network Processor Dram CH2 PMU Event List (Sheet 2 of 5)
Table 184. IXP2800 Network Processor Dram CH2 PMU Event List (Sheet 3 of 5)
Table 184. IXP2800 Network Processor Dram CH2 PMU Event List (Sheet 4 of 5)
11.4.6.31 IXP2800 Network Processor DRAM CH1 Events Target ID(010101) /
11.4.6.32 IXP2800 Network Processor DRAM CH0 Events Target ID(010110) /
Table 184. IXP2800 Network Processor Dram CH2 PMU Event List (Sheet 5 of 5)
Table 185. IXP2800 Network Processor Dram CH1 PMU Event List
Table 186. IXP2800 Network Processor Dram CH0 PMU Event List
