Intel IXP2800 5.5 Interleaving

Hardware Reference Manual 191
Intel® IXP2800 Network Processor
DRAM
5.5 Interleaving
The RDRAM channels are interleaved on 128-byte boundaries in hardware to improve
concurrency and bandwidth utilization. Contiguous addresses are directed to different channels by
rearranging the physical address bits in a programmable manner described in Section 5.5.1 through
Section 5.5.3 and then remapped as described in Section5.5.4. The block diagram in Figure 69
illustrates the flow.
The mapping of addresses to channels is completely transparent to software. Software deals with
physical addresses in RDRAM space; the mapping is done completely by hardware.
Note: Accessing an address above the amount of RDRAM populated will cause unpredictable results.
5.5.1 Three Channels Active (3-Way Interleave)
When all three channels are active, the interleave scheme selects the channel for each block, using
modulo-3 reduction (address bits [31:7] are summed as modulo-3, and the remainder is the selected
channel number). The algorithm ensures that adjacent blocks are mapped to different channels.
The address within the DRAM is then selected by rearranging the received address, as shown in
Table63. In this case, the number of DRAMs on a channel must be either 1, 2, 4, 8, 16, or 32.
For Rev. B, the address within the DRAM is selected by adding the received address to the contents
of one of the CSRs (K0 – K11), or 0, as shown in Table64. The values to load into K0 – K11 are a
function of the amount of memory on the channel, and are specified in the IXP2400 and IXP2800
Network Processor Programmer’s Reference Manual.
For memory sizes of 32, 64, or 128 Mbytes, etc., the specified constants give the same remapping
as was done in a previous revision.
Figure 69. Address Mapping Flow
In-Channel Address
Channel
Selection
Bank 0
CMD FIFO
Bank 1
CMD FIFO
Bank 2
CMD FIFO
Bank 3
CMD FIFO
Address
Remapping
Microengine, Intel
XScale® core, PCI-
initiated address
RDRAM_CONTROL[NO_CHAN] RDRAM_CONTROL[BANK_REMAP]