4Hardware Reference Manual
Contents
2.6 Scratchpad Memory............................................................................................................56
2.6.1 Scratchpad Atomic Operations..............................................................................57
2.6.2 Ring Commands....................................................................................................57
2.7 Media and Switch Fabric Interface ..................................................................................... 59
2.7.1 SPI-4................................................................................................... ...................60
2.7.2 CSIX...................................................................................................................... 61
2.7.3 Receive..................................................................................................................61
2.7.3.1 RBUF.................................... ................................................................. 62
2.7.3.1.1 SPI-4 and the RBUF....................................... .......................62
2.7.3.1.2 CSIX and RBUF..................................................................... 63
2.7.3.2 Full Element List...... ..............................................................................63
2.7.3.3 RX_THREAD_FREELIST............................................................ .......... 63
2.7.3.4 Receive Operation Summary................................................................. 64
2.7.4 Transmit............................................................................. .................................... 65
2.7.4.1 TBUF...................................................................................................... 65
2.7.4.1.1 SPI-4 and TBUF..................................................................... 66
2.7.4.1.2 CSIX and TBUF..................................... ................................67
2.7.4.2 Transmit Operation Summary................................................................ 67
2.7.5 The Flow Control Interface .................................................................................... 68
2.7.5.1 SPI-4......................................................................... ............................. 68
2.7.5.2 CSIX....................................................................................................... 68
2.8 Hash Unit.................................................................. ..........................................................69
2.9 PCI Controller....................................... ..............................................................................71
2.9.1 Target Access........................................................................ ................................71
2.9.2 Master Access......... .............................................................................................. 71
2.9.3 DMA Channels....................................................................................................... 71
2.9.3.1 DMA Descriptor...................................................................................... 72
2.9.3.2 DMA Channel Operation........................................................................ 73
2.9.3.3 DMA Channel End Operation...... ..........................................................74
2.9.3.4 Adding Descriptors to an Unterminated Chain.......................................74
2.9.4 Mailbox and Message Registers............................................................................ 74
2.9.5 PCI Arbiter............... .............................................................................................. 75
2.10 Control and Status Register Access Proxy......................................................................... 76
2.11 Intel XScale® Core Peripherals...... .................................................................................... 76
2.11.1 Interrupt Controller.................................................................................................76
2.11.2 Timers................................................................................................. ...................77
2.11.3 General Purpose I/O..............................................................................................77
2.11.4 Universal Asynchronous Receiver/Transmitter......................................................77
2.11.5 Slowport.......................................................................................... .......................77
2.12 I/O Latency..... .................................................................................................................... 78
2.13 Performance Monitor......................................... .................................................................78
3 Intel XScale® Core......................... ........................................................................... ................... 79
3.1 Introduction.................................................................. .......................................................79
3.2 Features.............................................................................................................................. 80
3.2.1 Multiply/ACcumulate (MAC)................................................................................... 80
3.2.2 Memory Management............................................................................... .............80
3.2.3 Instruction Cache................................................................... ................................81
3.2.4 Branch Target Buffer (BTB)............................ ....................................................... 81
3.2.5 Data Cache..................................................................... .......................................81
3.2.6 Performance Monitoring ........................................................................................ 81