Hardware Reference Manual 19
Contents
Tables
1 Data Terminology... .................................................................................................................... 26
2 Longword Formats................................................................................................ ......................26
3 IXP2800 Network Processor Microengine Bus Arrangement..................................................... 35
4 Next Neighbor Write as a Function of CTX_ENABLE[NN_MODE] ............................................38
5 Registers Used By Contexts in Context-Relative Addressing Mode ..........................................41
6 Align Value and Shift Amount.................................................................. ...................................43
7 Register Contents for Example 10.............................................................................................. 44
8 Register Contents for Example 11.............................................................................................. 45
9 RDRAM Sizes...................................................................................... .......................................50
10 SRAM Controller Configurations................................................................................................. 52
11 Total Memory per Channel..................................... ....................................................................53
12 Address Reference Order.............................................................................................. .............55
13 Q_array Entry Reference Order.................................................................................................. 55
14 Ring Full Signal Use – Number of Contexts and Length versus Ring Size................ ................58
15 TBUF SPI-4 Control Definition.............................................................................. ......................66
16 TBUF CSIX Control Definition ....................................................................................................67
17 DMA Descriptor Format....................................................................... .......................................72
18 Doorbell Interrupt Registers........................................................................................................ 75
19 I/O Latency ................................................................................................................................. 78
20 Data Cache and Buffer Behavior when X = 0.......................................................................... ...83
21 Data Cache and Buffer Behavior when X = 1.......................................................................... ...83
22 Memory Operations that Impose a Fence ..................................................................................84
23 Valid MMU and Data/Mini-Data Cache Combinations................................................................ 85
24 Performance Monitoring Events ...............................................................................................107
25 Some Common Uses of the PMU............................................................................................. 108
26 Branch Latency Penalty.............................................................................................. ..............112
27 Latency Example.............................. ........................................................................................114
28 Branch Instruction Timings (Predicted by the BTB).................................................................. 115
29 Branch Instruction Timings (Not Predicted by the BTB).......................... .................................115
30 Data Processing Instruction Timings................... .....................................................................115
31 Multiply Instruction Timings ......................................................................................................116
32 Multiply Implicit Accumulate Instruction Timings ......................................................................117
33 Implicit Accumulator Access Instruction Timings...................................................................... 117
34 Saturated Data Processing Instruction Timings........................................................................ 117
35 Status Register Access Instruction Timings .............................................................................118
36 Load and Store Instruction Timings......................................................... .................................118
37 Load and Store Multiple Instruction Timings............................................................................. 118
38 Semaphore Instruction Timings.................................................................. ..............................118
39 CP15 Register Access Instruction Timings............................................................................... 119
40 CP14 Register Access Instruction Timings............................................................................... 119
41 SWI Instruction Timings.............................................................................................. ..............119
42 Count Leading Zeros Instruction Timings............................................................. ....................119
43 Little-Endian Encoding................................................................................................ ..............120
44 Big-Endian Encoding..................................... ...........................................................................120
45 Byte-Enable Generation by the Intel XScale® Core for Byte Transfers in Little- and
Big-Endian Systems.. ............................................................................................................... 121
46 Byte-Enable Generation by the Intel XScale® Core for 16-Bit Data Transfers in Little-
and Big-Endian Systems.. ........................................................................................................123