230 Hardware Reference Manual
Intel® IXP2800 Network Processor
SHaC — Unit Expansion
If the Command Inlet FIFO becomes full, the Scratchpad controller sends a full signal to the
command arbiter that prevents it from sending further Scratchpad commands.
7.1.2.3.1 Scratchpad Commands
The basic read and write commands transfer from 1 – 16 longwords of data to/from the Scratchpad.
Reads
When a read command is at the head of the Command queue, the Push Arbiter is checked to see if
it has enough room for the data. If so, the Scratchpad RAM is read, and the data is sent to the Push
Arbiter one 32-bit word at a time (the Push_ID is updated for each word pushed). The Push Data is
sent to the specified destination.
The read data is placed on the S_Push bus, one 32-bit word at a time. If the master is a
Microengine, it is signaled that the command is complete during the last phase of the push bus
transfer. Other masters (Intel XScale® core and PCI) must count the number of data pushes to
know when the transfer is complete.
Writes
When a write command is at the head of the Command Inlet FIFO, signals are sent to the Pull
Arbiter. If there is room in the queue, the command is sent to the Command pipe.
When a write command is at the head of the Command pipe, the command waits for a signal from
the Pull Data FIFO, indicating that the data to be written is valid. Once the first longword is
received, the data is written on consecutive cycles to the Scratchpad RAM until the burst (up to 16
longwords) is completed.
If the master is a Microengine, it is signaled that the command is complete during the last pull bus
transfer. Other masters (Intel XScale® core and PCI) must count the number of data pulls to know
when the transfer is complete.
Atomic Operations
The Scratchpad supports the following atomic operations.
•bit set
•bit clear
•increment
•decrement
•add
•subtract
•swap
The Scratchpad does read-modify-writes for the atomic operations, and the pre-modified data also
can be returned, if desired. The atomic operations operate on a single longword. There is one cycle
between the read and write while the modification is done. In that cycle, no operation is done, so an
access cycle is lost.
When a read-modify-write command requiring pull data from a source is at the head of the
Command Inlet FIFO, a signal is generated and sent to the Pull Arbiter (if there is room).